Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
More Support Log In
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technology. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
As the subject suggests, there is a MOS in a subcircuit which I want to reference it to use it in extracting info during simulation like VDS etc.
Ex. a Mos named N0 is in the instance of the subcircuit named "inst1" which inturn is a part of a bigger subcircuit "Inst2" in the topLevel. So from the topLevel I would reference it like: "Inst2.inst1.XN0.M0". [Final use: .extract label=VDSN0 vds(Inst2.inst1.XN0.M0)]
The prefix of "X" and the suffix ".M0" I am able to obtain by some manipulation of cdf params, but I am stuck in finding the rest of the part (Inst2.Inst1).
If anyone could help, it would be nice.
Thanks and Regards,
It's probably geGetInstHier() that you want - this will tell you the hierarchical path down to the current cellView (from where you started - i.e. this assumes you pushed down through the hierarchy), and then you can add on the info for the selected instance to the end.
In reply to Andrew Beckett:
Thanks a lot. I just tested and I indeed needed exactly this.However, the assumption that the user will descend from the toplevel is obvious, but just in case someone (the user) opens the view separately, isn't there any fancy way to get the names of parent cellView and the parent above etc ?Regards,
In reply to Atul Dwivedi:
There is no information in a cellView to be able to find out what your parent is. You could (conceivably) search through every cellView in all the libraries in your cds.lib to find out any cellView that instantiates you, and then repeat this operation over and over again - this would be very slow, and also the likelihood would be that there are multiple instantiations of the block you've opened, and so how would you know which one was intended?
So it's not a sensible idea.