Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I got some error messages from 3-rd party tools like "xichip.xiip.ximid.m3", I wish to write a skill to descend into the last hier level and generate marker on the device m3, I plan to use the geSwitch to switch to the hier.
But when I parse the error message, I found the instance name is not match with the schematic, in schematic, the instance name is like "Ichip", "IIp", "IMID", etc., how to handle this kind of instance name? as you know, the spice netlist is case-insensitive, so the simulation tools always treat anythings as lower-case.
I also tried dbFindAnyInstByName, and found it is also case-sensitive, is there any skill function can read the instance name with case-insensitive? or even wildcard?
No. You'd have to search along cvId~>instances yourself.
Bear in mind that adding markers on the leaf cell may not make much sense if the problem does not occur on every occurence of that leaf cell...
Blues,First you can strip off the "x" prefix:
when(rexMatchp("^[Xx]" instName) instName=substring(instName 2) ;strip off first character (start at index 2) )
Then you can map its case this way:
foreach(inst cv~>instances when(instName == lowerCase(inst~>name) instName = inst~>name instId = inst ) )
If you are using IC61x (IC615, IC616 or ICADV121) then you can use the pcre* functions, the pcreCompile() function accepts an option for caseless matching: PCRE_CASELESS (0x00000001) which you can use perhaps in a single call without needing to strip off the leading 'x'?
Hope this helps.
In reply to skillUser:
Thank you all for the quick reply.
Looks like to search along the instances in cell view is the only solution, I have though it before, but I just afraid of the efficiency when the schematic is huge.