Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
Verification Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.
Participate in CDNLive
A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.
Come & Meet Us @ Events
A huge knowledge exchange platform for academia. We are looking for academic speakers to talk about their research to industry attendees.
Americas University Software Program
Join the 250+ qualified Americas member universities who have already incorporated Cadence EDA software into their classrooms and academic research projects.
EMEA University Software Program
In EMEA, Cadence works with EUROPRACTICE to ensure cost-effective availability of our extensive electronic design automation (EDA) tools for non-commercial activities.
Apply Now For Jobs
If you are a recent college graduate or a student looking for internship. Visit our exclusive job search page for interns and recent college graduate jobs.
Cadence is a Great Place to do great work
Learn more about our internship program and visit our careers page to do meaningful work and make a great impact.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
Overview All Courses Asia Pacific EMEANorth America
Instructor-led training [ILT] are live classes that are offered in our state-of-the-art classrooms at our worldwide training centers, at your site, or as a Virtual classroom.
Online Training is delivered over the web to let you proceed at your own pace, anytime and anywhere.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm working for rewriting the mos bulk connection but I'm not getting how to get only bulk connection information
I tried this command geGetEditCellView()~>sigNames..By this I'm getting all pins info also
In reply to Andrew Beckett:
Please can any one help me to do this code
"Code to detect PMOS and NMOS device in given schematic and
change/overwrite bulk connection of PMOS to vdd! and NMOS to vss! "
Here I'm struck at getting wire information of bulk to source connected mos with respect to PMOS
I have no idea what you're asking here. What does "rewriting the mos bulk connection" mean? Please ask clearer questions, as otherwise it's likely the question will just get ignored if nobody can understand it (as has presumably happened here).
In reply to Vaasu:
I've just found that you had two separate posts - the second one provided slightly more information than the first. For a start, it showed that you're trying to do this for a schematic. So I merged the two threads.
It's not going to be that easy, because in the picture you showed, there's a wire connecting the bulk to the source. You'd have to find any wire segments which are overlapping the bulk pin, and delete them (probably the best way). Then add a short wire stub with a wire label (vdd! or vss!) to connect them. None of this is going to be that easy - and it's hard for me to explain precisely how to do that without writing the code for you (which I'm not going to do, because it would be quite a lot of work to do a comprehensive solution, especially when I know so little about what you are trying to do and may have misinterpreted it; plus I don't have the time). Also, you might have written most of this already - I don't know.
There is a Solution Article (Solution 11597774) which contains parts of the sort of code that I think you would need for this, it is here. While it is not an exact match for what you are talking about, it does contain code that works from an instance (you have specific instances in mind which you can find in a schematic) and looks at an instance terminal to see if it is overlapped by a wire segment - in your case you are specifically looking for the bulk terminals.
Hopefully the solution code will provide a good starting point?
In reply to skillUser:
Thanks Andrew for giving feedback......
Whatever you understood the question is right. I choose that method only but I'm deteted the net
cid= geGetEditCellView()tid = setof(x cv~>terminals x~>name == "VDD")foreach( net_id tid~>net foreach( fig net_id~>figs dbDeleteObject(fig)
Is there any other best way to do this??
Again while reconnecting and generating label to only bulk became problem for me. While reconnecting i got bBox of mos by css()~>instTerms~>net~>figs~>bBox but next how to connect those is problem can anyone help me
For bulk only I want to create label for that I'm using schCreateWire how to use this command please help me
Thank you Lawrence for replying..
But I'm not able access that link can please help me to acces that link...
I'm attaching the code here. Basically the solution asks if it is possible to prevent users from explicitly wiring up inherited connection pins, and the answer seems to be 'no' but a schematic check procedure (e.g. part of the Check and Save step) might help by identifying and flagging such cases. The code is intended to find wires overlapping pins with inherited connection expressions associated with them - you will need to alter the code to meet your needs, but hopefully this would provide a good start?