Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
I'm generating a symbol from VHDL code using the tsg generator. Is it possible to modify the value of the symbol pin property "Signal Type" on a pin by pin basis from within the tsg file? The guidelines given in the TSG Symbol Description File Structure (comphelp/appB) appear to indicate that it is not possible. If it can be done, does anyone know the syntax; if not, is there any work around that doesn't involve editing the symbol afterwards?
Thanks for any and all help.
This doesn't appear to be supported and doesn't seem to have been requested either. I can see (from a quick look in the source code) that there appears to be the ability to set sigType, powerSensitivity and groundSensitivity but in the symbolProps section - which seems a bit odd to me, as these would always be pin-specific.
So please contact customer support - I think we'll need to enhance this.
That said, it would be easy enough to set the sigType attribute on the net for each terminal after the symbol has been created using SKILL.
In reply to Andrew Beckett:
Thanks for the reply; it confirms what I suspected. Yes, we have a SKILL script that modifies the property retrospectively, but it would obviously make more sense to do that modifying at symbol generation, so I'll put in an enhancement request.