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i am doing a project on synchronous fifo design using
verilog. below written is my coding. after simulation the waveform is
showing error regarding its not giving value of rdata_valid and is
showing a red line in waveform and due to it address is also not being
taken.i have attached the waveform also. the logic for write logic is
also not accepting the address(no change occurs while changing value of
read_ptr). i have attached my file with it so plz refer to it.
plz help me out in this. your guidance and solns will help me in completing my project work.
We really can't do your project for you. Doing it youself is how you will learn.
I will point out that the red lines in the waveform window, unless you've changed the default settings, are X's. I'll also point out that I noticed that your reset signal does not assign every internal variable to a starting value. Make sure your simulation starts with an assertion of reset, and make sure that every latched signal is indeed set to a 1 or 0 value by that reset. Any problems after that are yours to discover. Have fun!
In reply to TAM1:
thank you so much sir for your time and i appreciate your suggestion and will surely work upon it. i will surely contact you again in future if i feel that m not able to find a solution to my problem.