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I am very new to noise analysis when it comes to switched capacitor based system. In my system I have a comparator which goes into unity feedback mode with some frequency. I have also a capacitor which either connects from input of comparator and ground or input of comparator and input to be compared. Apart from that I have some set of capacitors which gets connected or disconnected to input of comparator and ground or input of comparator and some supply.
Apart from this, I have a bandgap charge which is being compared with input charge. I also have to look noise coming from there also.
I am interested to do noise analysis to this system. I have seen some thread, but I couldn't understand how should I go about this circuit. I would be very thankful , if someone can help me doing this.
PSS and PNoise are the answer here (most likely). You might want to take a look at Simulating switched-capacitor filters with SpectreRF.
In reply to Andrew Beckett:
Thank you for being always first to answer. I referred your attachment before putting my query. But this says, it takes only one clock. In my system multiple switchings are happening and that too at different rates. Pardon my ignorance if I am not able to understand the material you attached.
In reply to Abhishek D:
Multiple switching (and different phases) are OK, but different frequencies might present a problem. What are the frequencies in your system?
Following are the details-
1) Comparator goes to unity feedback and then openloop - 222.22k
2) There are some caps and they either get connected b/w input of comparator and Supply or Input of comparator and ground- 2MHz
3) There is one switched cap BGREF. When comparator goes in unity feedback, there is charge in the capacitors due to bandgap. When compartor goes into openloop , input gets connected and input charge is compared to bandgap charge. Depending on the difference, the comparator switches. No such defined frequency but should finish operation in the open loop mode of comparator.
If the frequency of the first clock has a period of 4.5us (so the period is 222.222222222k), then you could set that as your fundamental period in the PSS. Then the 0.5us period of the 2MHz clock would be exactly 1/9 of the other clock - and so you'd get a whole number of clock periods without too nasty a ratio and the simulation time should be reasonable.
I am less sure about the third point because it is not clear whether this would have a periodic behaviour. If that switches within the period of the 222.2222kHz clock I think it should be OK. Hard to tell without understanding the circuit in more detail.
Previously I gave some incorrect information. My flow is like that
1) Comparator sampling bandgap charge @ 400 Khz
2) Comparator sampling input charge @ 400 Khz but after 1. ( Phase lag )
2) Caps are connecting disconnecting @ 2 Mhz
In that case your fundamental frequency is 400kHz (actually, reading your second point, if that's 1 cycle lag, you may need 200kHz to include two cycles of the clock to capture the fact that you need two cycles to capture the period behaviour).