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I'd really appreciate if any of you could help me concerning following problem i'm facing using ADE-XL.
I designed a mixed signal circuit and I'd like to estimate the effect of mismatch on my analog part while using the functional view of the standard digital cells I used to manually design (with the schematic editor) my digital part.
I created a config view of my test bench with the ams template and then simulated it with ADE without any problem. I also have no problems if I simulate a "Single Run" of the same test bench with ADE-XL.
However when I switch to "Monte Carlo Sampling" the simulations complete but the results are weird, i.e. the digital block hasn'n worked properly.
I tried thus with a very simple test design (2-bit johnson counter with D-FF with asynchronous S and R and few analog components between Vdd and Gnd) and found out that by MC simulations the FFs enter in X state immediately after the initial Reset.
I thouhg I'd depend on the PDK's libraries, but I didn't got any good hint from our factory online support so I'd really appreciate any suggestion from your side.
Thank you in advance!
Cadence version: 184.108.40.2060.132
I think this will be quite hard to debug without seeing your data, so best if you can contact customer support.
In reply to Andrew Beckett: