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<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>AWR Design Environment - Recent Threads</title><link>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>RE: adding internal port to small loop antenna</title><link>https://community.cadence.com/thread/1408676?ContentTypeID=1</link><pubDate>Tue, 16 Jun 2026 07:31:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4f0031b3-2de7-46b4-8d0a-b2e1046462c4</guid><dc:creator>OscPn</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408676?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66062/adding-internal-port-to-small-loop-antenna/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Refer to&amp;nbsp;&lt;span&gt;AWR Design Environment Simulation and Analysis Guide, to know more about ports and it&amp;#39;s Application&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>adding internal port to small loop antenna</title><link>https://community.cadence.com/thread/66062?ContentTypeID=0</link><pubDate>Thu, 11 Jun 2026 09:55:11 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:edcbd5ad-4694-4a0e-9897-c62946776d7d</guid><dc:creator>AD202606089244</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/66062?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66062/adding-internal-port-to-small-loop-antenna/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;how to add internal port in design of small loop antenna after creating gap in ring structure? even after selecting option of add internal port, it does not get added at the required place..&lt;/p&gt;</description></item><item><title>RE: adding internal port to small loop antenna</title><link>https://community.cadence.com/thread/1408664?ContentTypeID=1</link><pubDate>Sat, 13 Jun 2026 07:05:17 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:80227b02-5196-4a69-a69a-8d2696000f78</guid><dc:creator>AD202606089244</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408664?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66062/adding-internal-port-to-small-loop-antenna/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thank you very much for your guidance and support through your reply. Apart from internal port, there is only edge port &amp;amp;&amp;nbsp; point port available in options. I could not see differential port or series port. As per your suggestion I also went through example of dipole antenna and I tried that one. After drawing a rectangle with thick metal layer, I added internal port to that rectangle in between its structure &amp;amp; simulated it. But it is not getting simulated. Kindly guide.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408663?ContentTypeID=1</link><pubDate>Fri, 12 Jun 2026 21:27:15 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fe0112b6-0ef6-41fd-bc8a-8eed250c0f38</guid><dc:creator>CurtisAWR</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408663?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;You can try using&amp;nbsp;the Analyst-MP application instead of through MWO.&amp;nbsp; In that program you can set up ports and run simulations without needing to start in MWO.&amp;nbsp; You would need specific Analyst-MP features in your license file, which I am assuming you have.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:360px;max-width:360px;" alt=" " src="https://community.cadence.com/resized-image/__size/720x720/__key/communityserver-discussions-components-files/113/Analyst_5F00_MP.png" /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>3D EM absorber simulation</title><link>https://community.cadence.com/thread/66025?ContentTypeID=0</link><pubDate>Mon, 01 Jun 2026 13:49:19 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3d0e9e2a-b9c7-40c7-a3c9-12ea3ec2e4c1</guid><dc:creator>rrlagic</dc:creator><slash:comments>7</slash:comments><comments>https://community.cadence.com/thread/66025?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello!&lt;/p&gt;
&lt;p&gt;Truing to enter AWR MWO simulations based on past experience and general knowledge seems to be pretty steep. On the other hand I could not find a similar example, so I could look into it first. So I am asking community to suggest example or the topics to be studied first.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I want to use AWR MWO to study microwaves reflection from surfaces, like m/w absorber being illuminated by plane wave as a very first problem. I see many examples for circuits simulations, here I&amp;#39;d like to learn, how to simulate kind of distributed system, ideally estimate its characteristics, like S11.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Please suggests initial steps.&amp;nbsp;&lt;/p&gt;</description></item><item><title>RE: adding internal port to small loop antenna</title><link>https://community.cadence.com/thread/1408660?ContentTypeID=1</link><pubDate>Fri, 12 Jun 2026 11:40:52 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d82c14eb-7cd8-4d4b-b197-c818ee09e00e</guid><dc:creator>OscPn</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408660?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66062/adding-internal-port-to-small-loop-antenna/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;In &lt;strong&gt;AXIEM&lt;/strong&gt;, internal ports are &lt;strong&gt;not intended to be placed across a physical gap&lt;/strong&gt; in a structure. An internal port represents an &lt;strong&gt;infinitesimally small (zero-length) connection&lt;/strong&gt;, so it cannot span a real geometric break such as the gap you created in the loop antenna.&lt;/p&gt;
&lt;p&gt;That is why, even after selecting the &lt;em&gt;&amp;ldquo;Add Internal Port&amp;rdquo;&lt;/em&gt; option, the port does not get added at the desired location across the gap&amp;mdash;the tool is behaving as designed.&lt;/p&gt;
&lt;h3&gt;Key Points:&lt;/h3&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Internal ports&lt;/strong&gt; are used to excite or probe current/voltage within a &lt;strong&gt;continuous conductive region&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;They &lt;strong&gt;cannot bridge a physical discontinuity&lt;/strong&gt; (like a gap in a ring or loop antenna).&lt;/li&gt;
&lt;li&gt;To better understand correct placement and polarity, it is recommended to &lt;strong&gt;review the AXIEM documentation on internal ports&lt;/strong&gt; and refer to the &lt;strong&gt;installed example &amp;ldquo;Dipole Antenna&amp;rdquo;&lt;/strong&gt;, which demonstrates proper usage.&lt;/li&gt;
&lt;/ul&gt;
&lt;h3&gt;Recommended Approach for Your Case:&lt;/h3&gt;
&lt;p&gt;If your goal is to model and excite a &lt;strong&gt;physical gap&lt;/strong&gt; in the loop structure, you should instead use:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Differential ports&lt;/strong&gt;, or&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;Series ports&lt;/strong&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;These port types are specifically designed to handle excitation across a &lt;strong&gt;finite gap&lt;/strong&gt; and will allow proper simulation of the antenna behavior.&lt;/p&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Layout Pin Names Property in AWRDE 25.1</title><link>https://community.cadence.com/thread/66066?ContentTypeID=0</link><pubDate>Fri, 12 Jun 2026 10:49:41 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2f0ea5b0-d8aa-4e78-8bc3-369d8da90cc0</guid><dc:creator>SandyRF</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66066?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66066/layout-pin-names-property-in-awrde-25-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;A new layout shape Pin Name property supports more complex pin connectivity configurations. Individual shapes or layout instances can be turned into physical pins in layout by setting the Pin Name parameters on the shape Properties dialog box Net Properties tab. This pin model is recommended for Virtuoso Studio RF users who want to create IP that is interoperable with Virtuoso Studio as the new pin model uses the same connectivity model that Virtuoso Studio uses.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/113/pastedimage1781281206420v1.png" alt=" " /&gt;&lt;/p&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408580?ContentTypeID=1</link><pubDate>Mon, 08 Jun 2026 07:24:43 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9c6d67b7-5ff5-4697-9a0c-bde3db2e5828</guid><dc:creator>OscPn</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408580?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;For port addition in Clarity, you may check following link:&lt;/p&gt;
&lt;p&gt;Article (20515591) Title: Port Overview: Clarity Layout Workbench and Clarity 3D Layout&lt;br /&gt;URL: &lt;a href="https://ask.cadence.com/ASK/article-viewer?id=a1OPP000000eUFV2A2&amp;amp;pageName=article-viewer"&gt;ask.cadence.com/.../article-viewer&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408575?ContentTypeID=1</link><pubDate>Sun, 07 Jun 2026 19:30:53 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:040f3ee1-045e-4cf2-bd03-0377727f7b8a</guid><dc:creator>rrlagic</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/1408575?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Well, I have spent couple days fighting through the interface with help of AI tools and whatever I do the last stop is defining the port. I have tried with Analyst, still available in my setup, with Clarity - I can produce layered substrate, define boundary conditions on side walls of the enclosure to make the wave TEM, but whatever I do - just can&amp;#39;t add excitation port at the top of the enclosure. Would appreciate if someone share their example or recipe. In my current mood if I hear that&amp;#39;s impossible to do might be a relief too.&lt;/p&gt;
&lt;p&gt;Thanks.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408553?ContentTypeID=1</link><pubDate>Wed, 03 Jun 2026 20:45:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59d482b0-0d6c-4e62-be63-9a237b802fab</guid><dc:creator>rrlagic</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408553?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thank you for this hint too. I guess I need some reading in that direction to proceed.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408551?ContentTypeID=1</link><pubDate>Wed, 03 Jun 2026 14:43:25 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f7bfffae-2be6-4556-97eb-8869413e3931</guid><dc:creator>CurtisAWR</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/1408551?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;The types of analysis you wish to do require a 3D EM solver, which (in the Cadence suite of tools) would be the Clarity 3D Workbench.&amp;nbsp; This is the tool you should be evaluating for this task.&lt;/p&gt;
&lt;p&gt;AWRDE is primarily an RF/Microwave circuit / system simulator.&amp;nbsp; It will seamlessly operate with other Cadence tools such as the Clarity 3D Workbench, so that the results of these external solvers can be used with the circuit / system simulations you do in AWRDE.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How Can AI Transform RF Design and Simulation for Next-Gen 6G Systems?</title><link>https://community.cadence.com/thread/66036?ContentTypeID=0</link><pubDate>Wed, 03 Jun 2026 09:42:35 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:eaf980fc-c95d-4dd1-a2ca-bf510556aef5</guid><dc:creator>OscPn</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66036?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66036/how-can-ai-transform-rf-design-and-simulation-for-next-gen-6g-systems/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;How can Artificial Intelligence be effectively applied to the simulation, modeling, and design of RF components and systems for 6G applications? Looking for insights, tools, experiences, and best practices from the community.&lt;/div&gt;</description></item><item><title>CPW ports definition, explicit ground and union of metals</title><link>https://community.cadence.com/thread/65897?ContentTypeID=0</link><pubDate>Fri, 03 Apr 2026 14:12:40 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ec563b8d-d47f-407d-b666-501f6a23f1cc</guid><dc:creator>Romolo Marcelli</dc:creator><slash:comments>9</slash:comments><comments>https://community.cadence.com/thread/65897?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/65897/cpw-ports-definition-explicit-ground-and-union-of-metals/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello to everybody.&lt;/p&gt;
&lt;p&gt;I have some concerns about the correct definition of ground in a CPW configuration defined within the AWR Microwave Office AXIEM simulator.&lt;/p&gt;
&lt;p&gt;In the past years, I received the suggestion to use differential ports, like &amp;quot;1&amp;quot; for the signal and &amp;quot;-1&amp;quot; for the lateral ground. Of course, the same for port &amp;quot;2&amp;quot; or others. Reading again a post on this Community I have seen that somebody suggests to use &amp;quot;1&amp;quot; for the signal and &amp;quot;2&amp;quot; for the lateral ports. So, is it the same or one is better than the other?&lt;/p&gt;
&lt;p&gt;Again, when a CPW grounded (GCPW) is studied, is it sufficient to use a metal on the bottom boundary or it must be connected to the surface using via holes to have the metal surfaces at the same potential, i.e., ground?&lt;/p&gt;
&lt;p&gt;To end, I noticed that adding pieces of metal and making the union of them does not involve a redefinition of the metal sheet as a whole, because if such a metal is close to the I/O ports of the CPW structures, I am forced in filling all the side with the &amp;quot;-1&amp;quot; port to confirm. It seems that apparently I have one metal sheet, but in fact putting a differential port where I added some metal maintains the memory of the past configuration, forcing me in extending the &amp;quot;-1&amp;quot; definition to such a ghost metal... like in the figure attached.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/113/pastedimage1775225361460v1.png" alt=" " /&gt;&lt;/p&gt;</description></item><item><title>RE: CPW ports definition, explicit ground and union of metals</title><link>https://community.cadence.com/thread/1408541?ContentTypeID=1</link><pubDate>Wed, 03 Jun 2026 09:33:58 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c486893f-f734-4554-9e67-b8cfe1b6a0d2</guid><dc:creator>Romolo Marcelli</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408541?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/65897/cpw-ports-definition-explicit-ground-and-union-of-metals/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thank you very much. This actually means that a CPWG probably needs a few via holes along the path to ensure the ground conditions.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CPW ports definition, explicit ground and union of metals</title><link>https://community.cadence.com/thread/1408539?ContentTypeID=1</link><pubDate>Wed, 03 Jun 2026 07:53:55 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e499ff22-a654-4d60-a40c-b09a1d717e31</guid><dc:creator>OscPn</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408539?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/65897/cpw-ports-definition-explicit-ground-and-union-of-metals/rss?ContentTypeId=0</wfw:commentRss><description>&lt;ul&gt;
&lt;li&gt;1.&amp;nbsp; No, this does not appear to be a software issue; it is related to the experimental setup. The software attempts to emulate the experimental conditions.&lt;/li&gt;
&lt;li&gt;2.&amp;nbsp; The boundary conditions defined in the experimental setup should be replicated in the software. For simulation purposes, a differential port is sufficient.&lt;/li&gt;
&lt;/ul&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408536?ContentTypeID=1</link><pubDate>Tue, 02 Jun 2026 16:37:14 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c5ab137a-9f86-49a6-bd59-77de0e0c0396</guid><dc:creator>rrlagic</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408536?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thanks for the hint. Digesting materials available on the net it looks that solver like Analyst is capable to solve scattering on the structure problem, while others are tailored to something like a circuit.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;My ultimate goal is to simulate normal and oblique incidence of plane wave onto complex multilayered surface made of dielectrics, metal patches, and probably lumped varactors between them, kind of smart surface. I am confident there will be challenges to reach the final goal, so I restrict myself to simpler problem of single material layer absorber, for which I could have analytical solution to verify.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;So yes, there was good hint to start with EM solver and observe boundary conditions for enclosure.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;What makes me stuck, is how do I perform measurement of such kind of structure? Say, at this point I&amp;#39;d like to have S11 at air-surface boundary at normal incidence. How do I set up that measurement? It looks that they require a port, and port in turn requires metal to be attached to. How do I define that? How could I define either normal or oblique incidence?&amp;nbsp;We are having really hard time learning the tool without relevant example.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Thanks in advance.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How do I choose the right simulator in AWR?</title><link>https://community.cadence.com/thread/1408525?ContentTypeID=1</link><pubDate>Tue, 02 Jun 2026 01:37:53 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8464e656-627b-41c4-bae7-b3d1bd814103</guid><dc:creator>CurtisAWR</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408525?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66014/how-do-i-choose-the-right-simulator-in-awr/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;1. I don&amp;rsquo;t know off-hand of any specific examples where switching between Default Linear and APLAC Linear shows a noticeable difference in results / performance. However, you can reference&amp;nbsp;&lt;a href="https://support.cadence.com/apex/techpubDocViewerPage?xmlName=awrsimulationanalysis.xml&amp;amp;title=AWR%20Design%20Environment%20Simulation%20and%20Analysis%20Guide%20--%20Using%20the%20Linear%20Simulator%20-%203.1.4%20APLAC%20Linear%20Subcircuit%20Caching&amp;amp;hash=UsingtheLinearSimulator-aplac_lin_cacheAPLACLinearSubcircuitCaching&amp;amp;c_version=25.1%20ISR5&amp;amp;path=awrSimulationAnalysis/awrSimulationAnalysis25.1_ISR5/Using_the_Linear_Simulator.html#UsingtheLinearSimulator-aplac_lin_cacheAPLACLinearSubcircuitCaching"&gt;this link&lt;/a&gt;&amp;nbsp;from the relevant section of the Help Manual to see where APLAC Linear Subcircuit Caching can specifically result in performance improvements.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;2. Note that Spectre will yield a simulation in Linux, and I think you said you are in Windows. MWO in Windows will indeed generate the netlist, but you would need the solver to generate the data simulation, and this is a Linux requirement.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;3. The Configuration menu reflects a list of Simulation Configurations available (either as the Default configuration, or specific Switch Lists, defined by the user). The best way for you to learn about them is to click the &amp;ldquo;Help&amp;rdquo; menu on that dialog, and on the resulting Help page, to click again on the Switch View Concepts link in the Configuration row of the table. See &lt;a href="https://support.cadence.com/apex/techpubDocViewerPage?xmlName=awrsimulationanalysis.xml&amp;amp;title=AWR%20Design%20Environment%20Simulation%20and%20Analysis%20Guide%20--%20Using%20Simulation%20Filters%20and%20Switch%20View%20Lists%20-%201.9%20Using%20Simulation%20Filters%20and%20Switch%20View%20Lists&amp;amp;hash=&amp;amp;c_version=25.1%20ISR5&amp;amp;path=awrSimulationAnalysis/awrSimulationAnalysis25.1_ISR5/Using_Simulation_Filters_and_Switch_View_Lists.html"&gt;this link&lt;/a&gt; for more information on how -- and why you might -- set up a Switch List.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How do I choose the right simulator in AWR?</title><link>https://community.cadence.com/thread/66014?ContentTypeID=0</link><pubDate>Thu, 28 May 2026 09:02:43 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9462740f-7fd9-42da-bc47-6319d31c2b3b</guid><dc:creator>AnalogMonk</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/66014?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66014/how-do-i-choose-the-right-simulator-in-awr/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi all,&lt;/p&gt;
&lt;p&gt;When I try to run a simple linear simulation, I see &lt;strong&gt;multiple simulator options&lt;/strong&gt; like:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Default Linear&lt;/li&gt;
&lt;li&gt;APLAC Linear&lt;/li&gt;
&lt;li&gt;Spectre Linear&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;At first glance, they all seem to do the &lt;em&gt;same thing&lt;/em&gt; (just linear simulation), but clearly they&amp;rsquo;re not identical.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;My questions:&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Is &lt;em&gt;Default Linear always enough&lt;/em&gt;, or should I be using APLAC/Spectre?&lt;/li&gt;
&lt;li&gt;Are these just different engines for the same math, or do they behave differently in practice?&lt;/li&gt;
&lt;li&gt;In what scenarios do you switch from one to another?&lt;/li&gt;
&lt;/ol&gt;</description></item><item><title>RE: 3D EM absorber simulation</title><link>https://community.cadence.com/thread/1408524?ContentTypeID=1</link><pubDate>Mon, 01 Jun 2026 23:30:19 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59c2b032-5c1e-444f-bc68-dd98114b9c6f</guid><dc:creator>CurtisAWR</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408524?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66025/3d-em-absorber-simulation/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I suspect you will need&amp;nbsp;an EM&amp;nbsp;solver like Analyst / Clarity, or at least AXIEM, to effectively model the effects of a lossy boundary like an absorber.&lt;/p&gt;
&lt;p&gt;You&amp;nbsp;could create a 3D EM Structure and then open its Enclosure node -- and then go to the Boundary Conditions Tab -- to set the way in which the structure&amp;#39;s boundaries are terminated.&amp;nbsp; You can of course set them as Open or Perfect Conductor, but you can also set them to be a material which you specifically define in the Material Defs. tab of the STACKUP.&lt;/p&gt;
&lt;p&gt;See screenshots below.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:337px;max-width:397px;" alt=" " height="337" src="https://community.cadence.com/resized-image/__size/794x674/__key/communityserver-discussions-components-files/113/Boundary_5F00_Conditions.png" width="397" /&gt;&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;img style="max-height:206px;max-width:319px;" alt=" " height="206" src="https://community.cadence.com/resized-image/__size/638x412/__key/communityserver-discussions-components-files/113/Material_5F00_Defs.png" width="319" /&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How do I choose the right simulator in AWR?</title><link>https://community.cadence.com/thread/1408516?ContentTypeID=1</link><pubDate>Mon, 01 Jun 2026 09:22:24 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7e0d4239-b78d-4ba1-9f7a-10f911257e77</guid><dc:creator>AnalogMonk</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408516?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66014/how-do-i-choose-the-right-simulator-in-awr/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thanks for sharing the details. I have few more questions related to this:&lt;/p&gt;
&lt;p&gt;1. Can you share a practical example where switching from the default linear simulator to APLAC resulted in a noticeable improvement in results or performances?&lt;/p&gt;
&lt;p&gt;2. When I select the spectre simulator on my windows machine it throws an error. However, I noticed that it generates a netlist (.scs). How did it generates without that solve? - snap attached&amp;nbsp;&lt;/p&gt;
&lt;p&gt;3. What is the purpose of &amp;#39;configuration&amp;#39; button in the simulator settings? Are there any scenario or measurement where we can change that?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CPW ports definition, explicit ground and union of metals</title><link>https://community.cadence.com/thread/1408502?ContentTypeID=1</link><pubDate>Fri, 29 May 2026 09:51:25 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3e21dc61-78ae-45bf-9ca7-838378bc9766</guid><dc:creator>Romolo Marcelli</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408502?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/65897/cpw-ports-definition-explicit-ground-and-union-of-metals/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi, I am still studying the differences between CPW and CPWG with Microwave Office AXIEM. Actually, for CPWG I solved the simulation problems using a number of via holes physically connecting the lateral ground plane on the top of the substrate with the bottom metal, to assure a ground to the studied structure. Nevertheless, I have a few conceptual problems: (1) the presence of via holes solved for me the comparison between a semi-lumped approach simulated circuitally (where the parameter GND=1 emulates the CPWG library elements) and the electromagnetic result; but, is this only a SW problem, or experimentally, I really need the via holes? (2) If I am simulating the simple CPW, is the differential port definition enough to have a &amp;quot;real&amp;quot; result, or do I also need more specific boundary conditions to try a direct comparison with the experiment?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: CPW ports definition, explicit ground and union of metals</title><link>https://community.cadence.com/thread/1408501?ContentTypeID=1</link><pubDate>Fri, 29 May 2026 09:51:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b0fccf94-d469-4c5d-a3d7-3ba14ecd21af</guid><dc:creator>Romolo Marcelli</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408501?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/65897/cpw-ports-definition-explicit-ground-and-union-of-metals/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi, I am still studying the differences between CPW and CPWG with Microwave Office AXIEM. Actually, for CPWG I solved the simulation problems using a number of via holes physically connecting the lateral ground plane on the top of the substrate with the bottom metal, to assure a ground to the studied structure. Nevertheless, I have a few conceptual problems: (1) the presence of via holes solved for me the comparison between a semi-lumped approach simulated circuitally (where the parameter GND=1 emulates the CPWG library elements) and the electromagnetic result; but, is this only a SW problem, or experimentally, I really need the via holes? (2) If I am simulating the simple CPW, is the differential port definition enough to have a &amp;quot;real&amp;quot; result, or do I also need more specific boundary conditions to try a direct comparison with the experiment?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How do I choose the right simulator in AWR?</title><link>https://community.cadence.com/thread/1408500?ContentTypeID=1</link><pubDate>Fri, 29 May 2026 08:21:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:aa4e3498-9691-4bac-9f08-a4641319efd3</guid><dc:creator>OscPn</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408500?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66014/how-do-i-choose-the-right-simulator-in-awr/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi&amp;nbsp; AnalogMonk,&lt;/p&gt;
&lt;p&gt;For most cases, the default Linear simulator is the fastest and best option.&lt;/p&gt;
&lt;p&gt;In some cases, APLAC Linear subcircuit caching can improve simulation time, so APLAC may be preferred.&lt;/p&gt;
&lt;p&gt;The Spectre solver is available only on Linux.&lt;/p&gt;
&lt;p&gt;Other solver engines are also available, such as APLAC HB in Microwave Office, and VSS has its own separate solvers.&lt;/p&gt;
&lt;p&gt;Depending on the application, you can switch between solvers, and each measurement in AWR automatically enables the appropriate solver.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Change license type on Linux for AWR Design Environment</title><link>https://community.cadence.com/thread/1408469?ContentTypeID=1</link><pubDate>Wed, 13 May 2026 10:00:21 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a4251511-5a1f-4937-8479-e5acb4b005e4</guid><dc:creator>OscPn</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408469?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66001/change-license-type-on-linux-for-awr-design-environment/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;For installing AWR on Linux, refer to the following article:&lt;/p&gt;
&lt;p&gt;Article (20519653) Title: Step-By-Step Guide to Install AWR 25.1 Release on Linux&lt;br /&gt;URL: &lt;a href="https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1OPP000001lbjV2AQ"&gt;support.cadence.com/.../ArticleAttachmentPortal&lt;/a&gt;&lt;/p&gt;
&lt;p&gt;Regarding license modifications, you can NOT make any changes directly in the license file. For your specific requirement, I recommend contacting the provider of your current license file or following the license file generation process while clearly outlining your requirement.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Change license type on Linux for AWR Design Environment</title><link>https://community.cadence.com/thread/66001?ContentTypeID=0</link><pubDate>Tue, 12 May 2026 17:31:27 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7e359fcc-696b-4d1a-aef7-2888f8433355</guid><dc:creator>DK202604288645</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66001?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/f/awr-design-environment/66001/change-license-type-on-linux-for-awr-design-environment/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I am looking to install&amp;nbsp;AWR Design Environment on Linux&amp;nbsp;and change the license type used from Standard to Flexnet.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Is there any way to do this? Without changing license I cannot use University License to launch the application.&lt;/p&gt;
&lt;p&gt;Thanks&lt;/p&gt;</description></item></channel></rss>