Is there a way to make Cadence point to the error?

Re: Is there a way to make Cadence point to the error?

linbo — Thu, 26 Apr 2012 20:34:46 GMT

Hi Tony,

You also need to consider which cell in terms of how close you are to the top level chip/IP in terms of hierarchy. It makes no sense to check density on a small cell. Typically density is checked on higher level cells or very large cells in terms of area. This is because density is considered over the entire die. A tiny cell may meet density but when placed into the chip the areas around it might be sparse and so you'll have a density issue.

Are you working on IP or the whole chip? Which process are you using?

Generally the older, larger geometry processes like .13 and above will have more forgiving density rules. Smaller processes like 65nm, 40nm, and below have much more stringent requirements and include multi level metal proximity rules.

If you're doing IP for an SOC then you'll need to take care with the edges of your IP where the abutting neighboring layouts are unknown.

Also be aware that the bounding box of cells also includes/surrounds the entirety of the labels/txt displays and can give you false errors if texts "hang out" outside the edges of actual active layers at the edge of your cell.

A good way to proceed is just visually check each metal layer over your entire layout and any large open areas, especially close to denser areas will have problems.

Finally all the large fabs provide density filling routines within Assura and/or Calibre so that you do not have to do this by hand. There's usually an elaborate suite of special "fill" metal layers, fill vias, and corollary blocking layers. Some fabs/processes (like Jazz) do the fill for you unless you request otherwise. Before spending a lot of time carefully making your layout meet density it might be good to check to see what your fab requirements are, what/where on the filling routines, and how to use.

Does this help?

Re: Is there a way to make Cadence point to the error?

Quek — Thu, 26 Apr 2012 14:14:32 GMT

Hi Tony

Total cell area means the rectangular bounding box created from all the objects in your cellview.There is no option which can display the bounding box.

Best regards
Quek

Re: Is there a way to make Cadence point to the error?

tony4tony — Thu, 26 Apr 2012 14:02:27 GMT

Hi Quek,

Playing with the options I found I can find the metal (or component dimensions) using Windows->Assistants->Property View.. But how do I calculate/find the total cell layout area? Is it by the normal area equation (length x breadth)? Or is there any option in the editor which tells what is the total area?

Thanks,

Tony

Re: Is there a way to make Cadence point to the error?

Quek — Thu, 26 Apr 2012 09:32:52 GMT

Hi Tony

For density errors, there is no single metal shape that is causing the violation. The error is a results of all the shapes. Let's go through the following example:

- You have 2 metal1 shapes in your layout.
- 1st metal1 shape has area of 1um2
- 2nd metal1 shape has area of 2um2
- Total cell layout is 10um2
- DRC density requirement is 50%

Using the total area of the shapes, your current density can be calculated as (1+2)/10 * 100% = 30%. Hence density error is reported during drc check. You cannot say that it is shape1 or shape2 that is causing the error. The error is a results of insufficient total metal1 area for the entire cell.

Best regards
Quek

Is there a way to make Cadence point to the error?

tony4tony — Thu, 26 Apr 2012 09:27:23 GMT

Hi Quek,

Thank you very much for the help. That is very helpful information. Is there an easy way to highlight in the layout editor which are the metal connectors which have violated the rules? Or do I have to go through each metal and see their properties?

Thanks,

Tony

Re: request to the administrators

Quek — Wed, 25 Apr 2012 22:54:26 GMT

Hi Tony

This is the correct forum. Every layout must meet certain density requirement so that it can be properly fabricated by the foundry. E.g. if the total area of your cellview is 10um2 ("um2" means micro-metre square) and you only a single piece of M1 metal with area 1um2, then it means that your M1 density is 100% * 1/10 = 10% and hence your cell fails the requirement of 30%.

Modern foundries use CMP (chemical mechanical polishing) processes to smoothen the surface of the wafers and if the density of each layer is not uniform, the polishing of the wafer would result in uneven wire thickness and hence changes the intended characteristics of the process.

You can read more about this from any IC design layout textbooks. E.g.
http://www.amazon.com/IC-Layout-Basics-Practical-Guide/dp/0071386254

Best regards
Quek

request to the administrators

tony4tony — Wed, 25 Apr 2012 10:52:34 GMT

If this is not the correct location for the post please put it under the correct forum.

Thanks,

Tony