I'm currently using Virtuoso XL version IC6.1.7-64b.500.6 to do custom analog layout. I'm fairly new to IC6, and I do not have any corresponding Cadence schematics for my layout.
I have three pins named VCCOK, VCCEXT, and BGGND respectively. Note, these are signal pins in this design, not power rails.
When I use the "Analog Adjust Cell Sides" feature, VXL moves these three pins to the top and bottom of the layout cell, but outside the cell extent for any other active area devices. It them wraps the cell with PRBoundary. The problem is, VXL places these pins so that the PRBoundary is then a pin's width larger than it should be on both the top and bottom of the cell. VXL also changes the placement status of these pins to "Placed" automatically. The default placement status of all pins is always set to "none" here.
If I manually set the placement status on these pins to "Fixed" or "Locked/Cover", the Analog Adjust Cell Sides tool does nothing, and refuses to adjust the PRBoundary. If I manually set the placement status on these pins to "Placed", the Analog Adjust Cell Sides tool ignores the setting, and moves them as if they were set to "None".
I'm guessing that due to each pin having either a "VCC" or "GND" somewhere in the name, the tool is automatically assuming these are power rails, and not just normal signal pins.
Is there a way to stop Analog Adjust Cell Sides from moving the above named pins differently than it handles regular IO pins?