Custom IC Design - Recent Threads

Closing Pegasus results viewer causes hierarchy return during Pegasus DRC

ED202602057731 — Thu, 13 Aug 2026 17:46:56 GMT

Situation: open a layout block in VirtuosoXl and descend one or more levels. run Pegasus DRC on the sub-block. When you close the DRC debugging tool, the hierarchy will snap back to the top-level that you opened. I'm sure this is a setting and it is just an annoyance, but if anyone has a solution, I would be grateful

Measure across sweep in MC and get results to yield table for each MC point

Aboubakr — Thu, 13 Aug 2026 17:22:11 GMT

Hi,

I’m wondering if there is a way to get a measurement of eval type “sweeps” in a MC run to measure across only the sweep variables but not MC sweeps, so that I get the result for each MC point still.

and of there is a way to select which variable to measure across, I know there is measureAcross() function but it doesn’t seem to what the name implies.

this discussion touched on the same topic near the end, and Andrew mentioned that there was no way to do that 3 years ago, any updates today ?

Monte-Carlo mean included in expressions

thank you,

Aboubakr

VIVA reload: black window

Martinsh — Mon, 10 Aug 2026 07:40:59 GMT

IC251 isr6. When transicient simulation is runing, plot signal works well, but if reload from VIVA menu File->Reload, all signal waveforms on the result window are removed. How to solve this problem?

psf format different when simulation is run from ADE or in command line

kkdesbois — Tue, 04 Aug 2026 09:21:17 GMT

Hello,
When I run a simulation from ADE, I can see in VIVA a wave for each net, even if the simulation is a DC without sweep.

If I run the simulation file runSimulation from the directory netlist created by ADE, in VIVA each net is a scalar now and can not be plotted

Any reason for that? What makes the creation of wave rather than a scalar?
Laurent.

Add MOM license key Error: TSMC PDK Tool Error : No setting file

GZ20260415257 — Tue, 04 Aug 2026 06:24:48 GMT

Hi Community,

I was trying use layout MOM cap and found license needed. And I tried to add MOM license as tutorial, error occured.

As the picture shows, "no setting file" error reported. I have no ideal about this error and cannot find any solution.

May I got some help?

Global Girds cannot be displayed.

JH202504237643 — Tue, 04 Aug 2026 03:21:20 GMT

Hello,

After I update the PDK，Global Girds cannot be displayed.

The Global Grids option is checked.

pdk version: v1.2_2p2a2.

Thanks,

Han

Auto Via in Edit-in-Place with metals on higher levels

PK202501238151 — Mon, 03 Aug 2026 09:36:33 GMT

Hello,

I am using auto-via to generate vias between overlapping metals. I often work in edit-in-place, which means that some of the metals might be on higher hierarchy levels. These are apparently not considered when using auto vias. Is there a way of getting this to work?

Unable to select Accuracy Defaults in spectre 25.1

VIRAJ PANCHAL — Sun, 02 Aug 2026 07:02:24 GMT

Hello community,

I've upgraded my spectre version from 23.1 to 25.1.

When I create a maestro view and add the new transient analysis, so in the analysis I can't able to select Accuracy Defaults (conservation, moderate and liberal)..!!

So my question, is that a spectre 25.1 tool issue or something else..? (In spectre 23.1 I can able to select Accuracy Defaults.)

Look into in below snapshot of spectre 25.1. The Accuracy Defaults is disable kind of thing.

- Viraj.

PCB substarte generation on virtuoso and EM simulation using EMX

usercp — Wed, 29 Jul 2026 08:23:54 GMT

I want PCB substarte generation on virtuoso like ads substarte editor. After that, EM simulation using EMX. I want to manually generate and set PCB substate, but I don't know this is possible using GPDK 45nm.

Regarding EMX document, we can generate EMX proc file to meet our wants, however it's not compatible with GPDK 45nm layer information..

Could you please help to share how to setup PCB substarte and EM simulation at virtuoso and EMX tool, or any proper tool..?

Can't skip devices inside subckt in Checks/Asserts

AD20260518228 — Mon, 27 Jul 2026 12:13:57 GMT

Hi everyone,

I'm having trouble with Checks/Asserts in ADE Explorer and could use some help.

What I need: check all bsim4 devices in the bandgap block with abs(vdsat) < 0.3, but skip any devices inside logic cells — for example, an "inv" cell.

My setup:

· sub = bandgap
· primitive = bsim4
· expr = abs(vdsat) < 0.3
· skip_dev_inside_subckt = inv

The violating devices in bandgap get flagged fine, but the ones inside the inv cell are not skipped at all. They still show up. I've tried both cell name and instance name for the skip, but it doesn't work.

Also, is there a way to highlight the violating devices right on the schematic from the Checks/Asserts results? Would save a lot of time.

Any ideas? Thanks.

How to measure phase margin through deepprobe.?

VIRAJ PANCHAL — Sat, 25 Jul 2026 15:38:36 GMT

Hello community,

I am doing the verification of one block. I want to measure the phase margin(PM) though stability analysis.

I know the method to measure the phase(i.e connect iprobe in feedback path). But my this circuit is complex, so I want to measure the PM from top level testbench so I am using the deepprobe and cds_thru to connect the signal.

but I am unable to measure PM. In maestro view I got error message in PM expression.

So my question is that is this a right method to measure PM. if it is right then which probe should I select in stability form.?

How to average a transient-noise iteration family before applying ymax() in ViVA/ADE?

Tifox — Wed, 22 Jul 2026 17:13:50 GMT

Hi,

I am running a transient simulation with:

A parametric sweep of the ADC Vin_1 input starting voltage (6 sweep points)
Transient noise enabled with 10 iterations for each sweep point

I have a waveform/expression called DNL_ADC12 that contains the DNL versus time (or sample number).

When I evaluate: ymax(DNL_ADC12)

I obtain, for each input voltage, a waveform whose X-axis is the iteration number and whose Y-axis is the maximum DNL found during that iteration.

I can then evaluate: average(ymax(DNL_ADC12))

which gives the average of the maximum DNL values across the 10 iterations for each input voltage.

However, this is not the quantity I am looking for.

I would like to:

Average the complete DNL waveform across the 10 transient-noise iterations, point-by-point.
Obtain a single averaged DNL waveform for each input voltage.
Apply ymax() to this averaged DNL waveform.

In other words, I want:

ymax( average_over_iterations( DNL_ADC12 ) )

and not:

average( ymax( DNL_ADC12 ) )

which appears to average the ymax over all iterations rather than average the iteration family members. I also tried some family-related functions, but could not find the correct ViVA expression.

Does anyone know the proper ViVA/ADE calculator function to average a transient-noise iteration family point-by-point before applying ymax()?

Thanks.

Thierry

Cannot Map Schematic Net After Running Quantus QRC

aalbason — Sat, 18 Jul 2026 01:35:03 GMT

Hello there,

I am seeing this warning when I try to probe a node post QRC:

*WARNING* (PARA-805) Cannot map schematic net /net31, because the calculated extracted name does not exist in the extracted view. This could be because the extracted view is incorrect or LVS has failed.

I passed LVS using Calibre LVS.

IC25.1-64b.ISR5.36

Quantus 25.1.0-p047

Any thoughts on this?

Thanks,
Alfonso

Automatically switch between "sparameter" view and "rfm" view

amitG22 — Wed, 15 Jul 2026 07:52:06 GMT

Hello Community,

When I generate sparameter files through EMX, EMX generates the sparameter views that is basically a touchstone file. There is in essence no separate schematic with a nport component. This works well except when you want to run transient simulation. Then, spectre tries to generate bbspice models for all these sparameter views. Now, I don't want spectre to generate its own models (why not is not relevant for my question). I want to generate my own RFM models and want spectre to use them during transient simulation without creating a separate schematic with a nport component and pointing to a rfm file. This is tedious and doesn't scale well when you are working on a big project.

My question is : Is it possible to do this with spectre in an elegant manner instead of all the tedious manual work?

A snapshot of the view generated by EMX :

If it indeed turns out that its possible to "hack" the normal WoW and force spectre to use my own RFM models then the following information may be handy : In the linux directory structure, I have a folder that is exactly the same as the name of the sparameter view. Within it, next to the sparam.snp file I have placed my sparam.rfm file.

Thanks in advance for all your tips/tricks and suggestions.

Regards,
Amit

Import def file , get wrong coordinate , it has 0.0005 offset (0.1645 to 0.165)

Charley Chen — Wed, 15 Jul 2026 03:30:22 GMT

Hi All,

I have a layout , draw a shape at 0.1645:35.056 ... , generate def as below , but when GUI -> Import - DEF In to verify ,
It get wrong coordinate , it has 0.0005 offset (0.1645 to 0.165) , but shape width is the same.

How to fix this problem?

DEF file partial net as below:

VERSION 5.8 ;
UNITS DISTANCE MICRONS 1000 ;
.....

PIND 10 ;

- VV + NET VV

+ DIRECTION INPUT

+ USE SIGNAL

+ PORT

+ LAYER ME1 ( 0.0000 0.0000) (76.0000 152.0000)

+ PLACED (164.5000 34904.000 ) N ;
.....

Thanks,
Charley

Markers covering the waveform itself

Mooh — Tue, 14 Jul 2026 06:40:49 GMT

Hi,

I am using plot templates in VIVa, however when I plot my waveforms, a large number of markers are automatically placed at each frequency point, which end up covering the waveforms themselves.

Currently, I have to move them manually one by one, which is very time-consuming. Is there a way to automatically reposition or hide the markers to avoid this overlap?

Thank you!

Viva label Expression

Mooh — Tue, 14 Jul 2026 06:33:14 GMT

Hi,

I have an Assembler expression that returns a value, and I would like to display it as a label in Virtuoso Visualization and Analysis (VIVa).

For example, I have an SP S11 simulation and I would like to show the current consumption as a label directly on the waveform window.

Is this possible? If so, could you guide me on how to achieve it?

Thank you!

Pegasus-Quantus for sky130

TT202604271919 — Sun, 12 Jul 2026 18:11:00 GMT

I encountered this error when extracting parasitic in sky130_release_0.1.0. Anyone may help me to solve this ?

Monte Carlo over design variable sweep in ADE XL

RA20250218276 — Wed, 08 Jul 2026 06:42:15 GMT

I am using virtuoso version 6.1.8

I am trying to do monte carlo simulation over a circuit. But to get the output, I need to sweep design variable.

Basically I need to sweep the design_variable and the output I intend to obtain is output(design_variable=1) - output(design_variable=0) and so on. I do this by creating an expression with EvalType("corners") so it is evaluated once after the sweep is complete.

I have also read several forum posts that says ADE XL Monte Carlo only supports measurement over corners, so I created 65 different corners each with different input.

Then I retrieve the output of each corner using leafValue(VT() "design_variable" ValueAtEachCorner) and use it as part of the output expression.

But when I do monte carlo on that, I get the plot of each output expression across mc_paramset instead of scalar value such as mean, stdev, max, min.

Technically, I can save the plot as csv and calculate mean, stdev, max, min and anything else I need. But are there other ways to do it? Perhaps using OCEAN script measurement?

Also, using leafValue() to retrieve the output of each corner does work, but are there better ways to get output result that needs design_variable sweep?

Stop the simulation after the GUI crash

dogman4 — Tue, 07 Jul 2026 04:40:32 GMT

Hi，friends

When running simulations with Assembler, the simulation session is interactive.1. I previously set `continueICRPRunOnAbruptGUIExit` to t. However, Virtuoso crashed before the interactive.1 simulation finished. After noticing issues with the partial results generated, I need to terminate the interactive.1 simulation.

How should I do this?

My virtuoso version: "@(#)$CDS: virtuoso version 6.1.8-64b 09/03/2024 19:11 (sjfhw316) $"
My spectre version: Version19.1.0.063 64bit--10 Aug 2019

Liberate for characterizing emerging transistor technology

CW202607067723 — Mon, 06 Jul 2026 18:58:47 GMT

Hi there,

I'm developing a PDK/library for an emerging transistor technology. I've developed and validated a level-61 spice model for the transistors (non-Si-based) and the model can run in Spectre. The next step is to build standard cells for logic gates, characterize them, and generate .lib timing/power models for use in digital design and system-level evaluation.

I'm new to Liberate and was wondering if it is the right tool for this task. In particular:

Can Liberate characterize custom transistor-level cells using Spectre with a Level-61 device model? My understanding is Liberate should not depend on the internal transistor technology of the cell. As long as the Level-61 model is supported by Spectre, and Liberate can invoke Spectre on the transistor-level netlists, Liberate should be able to characterize the cells. Is that correct?
Can I start with schematic-level/pre-layout netlists, and later move to PEX-extracted netlists?

Any guidance or pointers would be greatly appreciated. Many thanks!

All the best,
Kevin

One schematic for multiple layouts

M202602061138 — Mon, 06 Jul 2026 14:19:49 GMT

What is the best way to handle multiple layouts of different aspect ratios using the same schematic when using LayoutXL?

We don't really want to duplicate the same schematic multiple times, but we do want layout XL to pass through the correct chosen aspect ratio and to maintain that layout when you do an update components and nets.

eg: circuit1 is used in 3 different locations with different shape/size areas available so requires 3 different layouts, layout_A, layout_B & layout_C

Would it be best to make it a pcell with Callback and CDF Parameters or use physConfig or another method?

Regards

Mike V.

ADE Explorer: How to pass a design variable to a parameter array and another design variable as a string parameter to an instance - Spectre vs. AMS

Volker T — Thu, 02 Jul 2026 10:26:53 GMT

Hi,

I am referring to the following two blog posts, both dealing with ADE Explorer and/or Spectre, as an introduction to a similar problem I have with ADE Explorer and AMS.

ADE Explorer and Spectre

1. How to Pass a String Design Parameter to a Cell

2. Defining Verilog-A vector in the maestro view

The first deals with the issue that when we have a parameterizable cell, like e.g. an instance "myInstance" of a cell using a Verilog-A view, that has a string parameter, e.g. "fname" that we want to specify by design variable, the Spectre netlist does not contain the value of the design variable, but its name only.

Example:

At the beginning of the Spectre netlist, we see the parameters passed to Spectre, e.g.

parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we only see

myInstance trise=trise tfall=trise tdelay=0 \
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile="fname"

So, instead of our string defined by design variable value, we only see the design variable name as a string passed to the instance's string parameter "logfile",

The solution shown by Andrew Beckett suggests to use SKILL functions to remove the respective string parameter while leaving the other string parameters in place:

almGetStringParameterList("mylib" "mycell" ?view "veriloga")

=> (fname someOtherParam somethingElse)

almSetStringParameterList("mylib" "mycell" '(someOtherParam somethingElse) ?view "veriloga")

=> (someOtherParam somethingElse)

The former function identifies all string parameters used by the respective view of a cell of a library (fname, someOtherParam and somethingElse in the example shown) and then the latter function can be used to set the same list minus the string parameter we would like to pass by design variable (e.g. fname) as the new string parameter list. That way, our Spectre netlist gets the value of the string parameter, and not only its name.

Now the beginning of the Spectre netlist still looks like this:

parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we now see

myInstance trise=trise tfall=trise tdelay=0 \
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname

So, instead of "fname" (in quotes, hence being a string), we only see fname without quotes, hence referencing the respective Spectre parameter.

Problem solved, instance parameter "logfile" is now fed by Spectre parameter "fname" containing string value "/tmp/mylogfile.log" of design variable "fname"..

The second post deals with parameter arrays. Again, let's assume we use an instance of a cell using a Verilog-A view, that has a parameter array, like

parameter integer pattern[2:0] = {1, 2, 3};

and we would like to use a design variable "myPattern" for the definition of the pattern, in ADE, then we cannot just enter [4 5 6] for that design variable value to define a new pattern, as ADE interprets that as a literal or SKILL code.

Andrew Beckett shows the solution for this in the referenced post #2, namely to use strcat("[4 5 6]") as design variable value instead. This gives valid SKILL code for ADE, translates into string "[4 5 6]", which translates into Spectre parameter [4 5 6].

Example:

At the beginning of the Spectre netlist, the parameter list now is

parameters myPattern=[4 5 6] vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

Later, when the respective instance occurs in the netlist, we see something like

myInstance trise=trise tfall=trise tdelay=0 pattern=myPattern\
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname

So, similar to the string parameter described before, the instance parameter now gets assigned the correct Spectre parameter.

So far, so good, problems solved for ADE Explorer and Spectre.

ADE Explorer and AMS

Now let's use the same test bench, using the same cells and design parameters, but AMS as a simulator. As far as I know, AMS uses a different netlister (UNL?), and that apparently behaves differently.

The instance now gets its parameters assigned like this

myInstance #(.trise(cds_globals.trise), .pattern("myPattern") .tperiod(cds_globals.tperiod), .tsdelay(cds_globals.tsdelay), .vdd(cds_globals.vdd50), .tdelay(0), .tfall(cds_globals.trise), .logfile("fname"), .debuglevel(cds_globals.debuglevel)) I1 (.nrst( nreset ), .mclk( mclk ), ... );

There is no "pre-translation" of design variables into AMS parameters to be found as a list (but apparently there exists one, named "cds_globals", as one can see for the other parameters). But both the string parameter and the array parameter do not show up in cds_globals but are used directly as a string containing the design variable name instead of its value.

So the question is, is there any trick similar to the two shown for Spectre that we can create a netlist using design variable values instead of design variable names?

Schematic generation form spice file

VIRAJ PANCHAL — Tue, 30 Jun 2026 14:11:27 GMT

Hi everyone,

I am trying to generate schematic from spice(.spi) file through import spice option in virtuoso. But during schematic generation process I faced below error massage.

*WARNING* (DB-270211): dbOpenCellViewByType: Cannot open cellview 'testLIB/DFCNQD1BWP6TSA16P96CPD/schematic' in 'a' mode because it does not exist or viewTypeName required to create a new cellview is not specified. Ensure that the cellview exists or to create a new cellview by specifying viewTypeName. Valid values for viewTypeName are "netlist", "schematic", "schematicSymbol" and "maskLayout".

According to above screenshot, The schematic view is not found in testLIB library. But how does it found before the schematic generation..!!?? It only give the netlist_tmp (blank schematic) as output but it should be schematic as output file.

Kindly anyone tell me what's the issue.!?

Parasitic extraction with StarRC

Phd SA88 — Tue, 30 Jun 2026 11:05:00 GMT

Deal all,

I would lik to do parasitic extration with StarRC. Thus, when opening the StarRC Parasitic view genaration, i added correctly all paths, as seen below:

Furthermore, i edit correctly both of file .snp_settings and the starrcxt.cmd. However when i click on apply, there is an error:

ERROR: MAPPING_FILE /working_directory/est3/STAR/LVS/calibrestar.map cannot be found.

So, the svdb folder and the calibrestar.map are not created which ensure that LVS does not occured;

Please help me to resolve this problem and thank you in advance

Best Regards