Custom IC Design - Recent Threads

Monte Carlo over design variable sweep in ADE XL

RA20250218276 — Wed, 08 Jul 2026 06:42:15 GMT

I am using virtuoso version 6.1.8

I am trying to do monte carlo simulation over a circuit. But to get the output, I need to sweep design variable.

Basically I need to sweep the design_variable and the output I intend to obtain is output(design_variable=1) - output(design_variable=0) and so on. I do this by creating an expression with EvalType("corners") so it is evaluated once after the sweep is complete.

I have also read several forum posts that says ADE XL Monte Carlo only supports measurement over corners, so I created 65 different corners each with different input.

Then I retrieve the output of each corner using leafValue(VT() "design_variable" ValueAtEachCorner) and use it as part of the output expression.

But when I do monte carlo on that, I get the plot of each output expression across mc_paramset instead of scalar value such as mean, stdev, max, min.

Technically, I can save the plot as csv and calculate mean, stdev, max, min and anything else I need. But are there other ways to do it? Perhaps using OCEAN script measurement?

Also, using leafValue() to retrieve the output of each corner does work, but are there better ways to get output result that needs design_variable sweep?

Stop the simulation after the GUI crash

dogman4 — Tue, 07 Jul 2026 04:40:32 GMT

Hi，friends

When running simulations with Assembler, the simulation session is interactive.1. I previously set `continueICRPRunOnAbruptGUIExit` to t. However, Virtuoso crashed before the interactive.1 simulation finished. After noticing issues with the partial results generated, I need to terminate the interactive.1 simulation.

How should I do this?

My virtuoso version: "@(#)$CDS: virtuoso version 6.1.8-64b 09/03/2024 19:11 (sjfhw316) $"
My spectre version: Version19.1.0.063 64bit--10 Aug 2019

Liberate for characterizing emerging transistor technology

CW202607067723 — Mon, 06 Jul 2026 18:58:47 GMT

Hi there,

I'm developing a PDK/library for an emerging transistor technology. I've developed and validated a level-61 spice model for the transistors (non-Si-based) and the model can run in Spectre. The next step is to build standard cells for logic gates, characterize them, and generate .lib timing/power models for use in digital design and system-level evaluation.

I'm new to Liberate and was wondering if it is the right tool for this task. In particular:

Can Liberate characterize custom transistor-level cells using Spectre with a Level-61 device model? My understanding is Liberate should not depend on the internal transistor technology of the cell. As long as the Level-61 model is supported by Spectre, and Liberate can invoke Spectre on the transistor-level netlists, Liberate should be able to characterize the cells. Is that correct?
Can I start with schematic-level/pre-layout netlists, and later move to PEX-extracted netlists?

Any guidance or pointers would be greatly appreciated. Many thanks!

All the best,
Kevin

One schematic for multiple layouts

M202602061138 — Mon, 06 Jul 2026 14:19:49 GMT

What is the best way to handle multiple layouts of different aspect ratios using the same schematic when using LayoutXL?

We don't really want to duplicate the same schematic multiple times, but we do want layout XL to pass through the correct chosen aspect ratio and to maintain that layout when you do an update components and nets.

eg: circuit1 is used in 3 different locations with different shape/size areas available so requires 3 different layouts, layout_A, layout_B & layout_C

Would it be best to make it a pcell with Callback and CDF Parameters or use physConfig or another method?

Regards

Mike V.

ADE Explorer: How to pass a design variable to a parameter array and another design variable as a string parameter to an instance - Spectre vs. AMS

Volker T — Thu, 02 Jul 2026 10:26:53 GMT

Hi,

I am referring to the following two blog posts, both dealing with ADE Explorer and/or Spectre, as an introduction to a similar problem I have with ADE Explorer and AMS.

ADE Explorer and Spectre

1. How to Pass a String Design Parameter to a Cell

2. Defining Verilog-A vector in the maestro view

The first deals with the issue that when we have a parameterizable cell, like e.g. an instance "myInstance" of a cell using a Verilog-A view, that has a string parameter, e.g. "fname" that we want to specify by design variable, the Spectre netlist does not contain the value of the design variable, but its name only.

Example:

At the beginning of the Spectre netlist, we see the parameters passed to Spectre, e.g.

parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we only see

myInstance trise=trise tfall=trise tdelay=0 \
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile="fname"

So, instead of our string defined by design variable value, we only see the design variable name as a string passed to the instance's string parameter "logfile",

The solution shown by Andrew Beckett suggests to use SKILL functions to remove the respective string parameter while leaving the other string parameters in place:

almGetStringParameterList("mylib" "mycell" ?view "veriloga")

=> (fname someOtherParam somethingElse)

almSetStringParameterList("mylib" "mycell" '(someOtherParam somethingElse) ?view "veriloga")

=> (someOtherParam somethingElse)

The former function identifies all string parameters used by the respective view of a cell of a library (fname, someOtherParam and somethingElse in the example shown) and then the latter function can be used to set the same list minus the string parameter we would like to pass by design variable (e.g. fname) as the new string parameter list. That way, our Spectre netlist gets the value of the string parameter, and not only its name.

Now the beginning of the Spectre netlist still looks like this:

parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we now see

myInstance trise=trise tfall=trise tdelay=0 \
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname

So, instead of "fname" (in quotes, hence being a string), we only see fname without quotes, hence referencing the respective Spectre parameter.

Problem solved, instance parameter "logfile" is now fed by Spectre parameter "fname" containing string value "/tmp/mylogfile.log" of design variable "fname"..

The second post deals with parameter arrays. Again, let's assume we use an instance of a cell using a Verilog-A view, that has a parameter array, like

parameter integer pattern[2:0] = {1, 2, 3};

and we would like to use a design variable "myPattern" for the definition of the pattern, in ADE, then we cannot just enter [4 5 6] for that design variable value to define a new pattern, as ADE interprets that as a literal or SKILL code.

Andrew Beckett shows the solution for this in the referenced post #2, namely to use strcat("[4 5 6]") as design variable value instead. This gives valid SKILL code for ADE, translates into string "[4 5 6]", which translates into Spectre parameter [4 5 6].

Example:

At the beginning of the Spectre netlist, the parameter list now is

parameters myPattern=[4 5 6] vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

Later, when the respective instance occurs in the netlist, we see something like

myInstance trise=trise tfall=trise tdelay=0 pattern=myPattern\
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname

So, similar to the string parameter described before, the instance parameter now gets assigned the correct Spectre parameter.

So far, so good, problems solved for ADE Explorer and Spectre.

ADE Explorer and AMS

Now let's use the same test bench, using the same cells and design parameters, but AMS as a simulator. As far as I know, AMS uses a different netlister (UNL?), and that apparently behaves differently.

The instance now gets its parameters assigned like this

myInstance #(.trise(cds_globals.trise), .pattern("myPattern") .tperiod(cds_globals.tperiod), .tsdelay(cds_globals.tsdelay), .vdd(cds_globals.vdd50), .tdelay(0), .tfall(cds_globals.trise), .logfile("fname"), .debuglevel(cds_globals.debuglevel)) I1 (.nrst( nreset ), .mclk( mclk ), ... );

There is no "pre-translation" of design variables into AMS parameters to be found as a list (but apparently there exists one, named "cds_globals", as one can see for the other parameters). But both the string parameter and the array parameter do not show up in cds_globals but are used directly as a string containing the design variable name instead of its value.

So the question is, is there any trick similar to the two shown for Spectre that we can create a netlist using design variable values instead of design variable names?

Schematic generation form spice file

VIRAJ PANCHAL — Tue, 30 Jun 2026 14:11:27 GMT

Hi everyone,

I am trying to generate schematic from spice(.spi) file through import spice option in virtuoso. But during schematic generation process I faced below error massage.

*WARNING* (DB-270211): dbOpenCellViewByType: Cannot open cellview 'testLIB/DFCNQD1BWP6TSA16P96CPD/schematic' in 'a' mode because it does not exist or viewTypeName required to create a new cellview is not specified. Ensure that the cellview exists or to create a new cellview by specifying viewTypeName. Valid values for viewTypeName are "netlist", "schematic", "schematicSymbol" and "maskLayout".

According to above screenshot, The schematic view is not found in testLIB library. But how does it found before the schematic generation..!!?? It only give the netlist_tmp (blank schematic) as output but it should be schematic as output file.

Kindly anyone tell me what's the issue.!?

Parasitic extraction with StarRC

Phd SA88 — Tue, 30 Jun 2026 11:05:00 GMT

Deal all,

I would lik to do parasitic extration with StarRC. Thus, when opening the StarRC Parasitic view genaration, i added correctly all paths, as seen below:

Furthermore, i edit correctly both of file .snp_settings and the starrcxt.cmd. However when i click on apply, there is an error:

ERROR: MAPPING_FILE /working_directory/est3/STAR/LVS/calibrestar.map cannot be found.

So, the svdb folder and the calibrestar.map are not created which ensure that LVS does not occured;

Please help me to resolve this problem and thank you in advance

Best Regards

Efficient iterative methods for threshold extraction (ex: extraction of the input referred offset voltage of a clocked comparator or the calibration code of a bandgap etc.)

baltaci — Tue, 30 Jun 2026 08:30:13 GMT

Hi all,

I would like to ask whether there are recommended methodologies for efficiently extracting a threshold condition that is otherwise defined implicitly and would normally require fine parameter sweeps.

Two representative examples where this arises:

In a clocked regenerative comparator, the input-referred offset is defined as the differential input at which the system switches state. A brute-force sweep over the input requires increasingly fine resolution, and the number of simulations grows rapidly as the desired error tolerance is reduced.
In DC operating-point calibration problems such as bandgap temperature compensation code tuning, the target digital calibration word is typically found by iterating until a target operating point is reached (or by finding the minimum slope). A full sweep over all possible codes is inefficient, whereas a successive-approximation approach can converge in logarithmic time.

In both cases, the brute-force approach can be viewed as a linear (or effectively rapidly growing) search:

for each candidate value → run simulation → evaluate condition → continue sweep

where achieving higher accuracy directly translates into a large increase in simulation count.

Instead, a more efficient formulation would be an iterative search (such as SAR):

initialize upper and lower bounds
while error > tolerance:
- select midpoint
- run simulation
- update bounds based on result

which reduces the number of simulations from linear scaling to logarithmic scaling with respect to resolution.

Are such successive-approximation style extraction methods considered standard practice for this class of problems? In particular, are they supported or commonly used within verification flows (including GUI-driven environments such as Assembler), especially when Monte Carlo mismatch analysis is involved where each sample may require an inner convergence loop for each iteration?

Additionally, I would like to ask whether an Ocean scripting-based solution is typically used for implementing such iterative flows. If so, is there guidance or best practice on ensuring that such scripted approaches remain competitive in runtime compared to traditional sweep-based methods, especially when combined with Monte Carlo mismatch simulations?

Thanks in advance.

Can

ERROR WHEN PRESS QUANTUS SETUP FORUM

RM202605273230 — Mon, 29 Jun 2026 17:33:45 GMT

Hello

for post layout simulation i wanted to extact layout netlist when i press quantus setup it shows *Error* eval: unbound variable - tabField in log box could you please help me to fix this error

Thank you

Recommended methodology for PSRR characterization of a clocked regenerative comparator

baltaci — Mon, 29 Jun 2026 07:41:22 GMT

Hi all,

I am trying to characterize the PSRR of a clocked regenerative comparator (StrongARM-type latch), and I am struggling not only with the simulator setup itself but also with the definition of PSRR for a latched comparator.

For switched-cap amplifiers and other periodically time-varying but small-signal linear circuits, the usual SpectreRF flow (PSS followed by PAC/PXF) makes sense because the circuit can be linearized around its periodic operating point and the output is a continuous analog quantity.

A regenerative comparator seems fundamentally different. Around the decision point, the small-signal gain becomes extremely large, and the final output is binary (either 0 or VDD). A very small perturbation in the input or supply can completely change the final decision. Because of this, I am having difficulty understanding what an "output-referred PSRR" would even mean.

My concern is that a PSS+PXF flow may not provide a meaningful PSRR metric in this case, unless there is a specific methodology or interpretation that I am missing.

Intuitively, it seems that supply noise should manifest itself as one of the following:

An input-referred offset shift (equivalent input error due to supply variation),
A change in decision time,
A change in metastability probability or decision error rate.

So my questions are:

Can PSS/PAC/PXF be meaningfully applied to this type of circuit, and if so, how should the results be interpreted?
Is there a recommended Cadence/SpectreRF methodology for characterizing supply sensitivity of a clocked comparator?

I would appreciate any guidance or references on how others typically characterize PSRR or supply sensitivity for dynamic comparators.

Thanks in advance.

Can

noise summary missing after pnoise simulation

gangliurfic — Sun, 28 Jun 2026 05:26:31 GMT

Hi,

I run a PSS+Pnoise simulation and saved results. Usually after the simulation is done, I can Print-Noise Summary to show the contributions.

Right now after my simulation, when I do this, I get an error

ERROR (EXPLORER-2404): Cannot find a setup database entry for handle 0.
Provide a valid database handle and try again.

*Error* error: Cannot find a setup database entry for handle 0. - nil

Also, the noisesummary folder is missing in the results directory.

Any idea why this is happening?

I am using IC25.1 ISR4.

Thanks.

PEX Results Much Worse Than Schematic Simulation

AVAQ Semi — Thu, 25 Jun 2026 08:41:59 GMT

Hi everyone,

I am working on a low-noise analog amplifier in Virtuoso and recently completed the layout.

The schematic simulation results look good and meet the target specifications. However, after running parasitic extraction (PEX) and re-simulating the extracted view, I observed a much larger gain degradation than expected. The DC operating points remain almost unchanged, but the AC gain drops by around 20%.

I have already checked:

Device sizes and connections
LVS clean
No obvious extraction errors
Same simulation setup between schematic and extracted views

My understanding is that interconnect parasitics should introduce some degradation, but this amount seems excessive.

For those with experience in analog layout and PEX analysis:

1. What are the most common causes of unexpectedly large gain reduction after extraction?
2. How do you usually identify which parasitic components are contributing the most?
3. Are there recommended debugging techniques within Virtuoso or Spectre to isolate the dominant parasitic effects?

Any suggestions would be greatly appreciated.

Thanks.

Replacing DSPF sub-circuits with their functional view in the Hierarchical Editor for an AMS Mixed-Signal Simulation

Josch — Mon, 22 Jun 2026 09:23:32 GMT

Hello Everyone,

I'm trying to optimise our design flow by better utilizing AMS simulation capabilities to decrease our simulation times. We work with Analog-On-Top and have smaller digital blocks in our analog blocks (config, pattern generators, etc...). I figured out how to this with schematic simulation or hierarchical av_extraced views. In both cases the individual blocks are discovered by the Hierarchical Editor and I can select in which way I want to simulate them (functional, schematic or av_extracted).

However our main workflow is DSPF based and I cannot get it working in such a way, that the Hierarchical Editor can detect the sub-block hierarchy in the hierarchical DSPF file. When I switch the top level block to DSPF and reload, all sub-blocks in the tree list disappear. I tried reading in the DSPF directly from the Hierarchical Editor menu and loading it as a DSPF cell view. The DSPF is hierarchical and has all the sub-blocks I care about defined as sub-circuits. I am using Calibre v2024.4_27.13, Quantus 24.1.0-p089 and Virtuoso IC23.1-64b.ISR17.40.

Is the av_extracted AMS Hierarchical Editor flow with a DSPF possible at all? If it's doable what could be the problem? If not what would be the correct approach? I also saw the documentation about DSPF-in-the-Middle (DSPFIM). Should this be used with DSPFs instead of the Hierarchical Editor?

I've also tried looking into IDSPF, but it seems like a hierarchical extraction is not possible in that format.

Thank you very much for your support.

Best,
Josch

How to use 500 bit conversion analog to digital expression

RM202605273230 — Tue, 16 Jun 2026 14:25:06 GMT

Hello

I am trying to convert 500 bits from analog.to digital and use in expression in Adexl.bit its taking upto 149 only how to use 500 directly could you please let me know Thank you

In Cadence Maestro, I want to create a calculator function

Mooh — Tue, 16 Jun 2026 05:17:32 GMT

In Cadence Maestro, I want to create a calculator function. I want the function to plot a vcsv file; it takes the path of the file and plots it as simply as that

variable for number of iterated instances

Volker T — Thu, 11 Jun 2026 14:56:10 GMT

I am referring here to post "Can I use a variable for number of iterated instances".

There is now a solution to change the number of instances of an instance array using "Window -> Assistants -> Variables and Parameters. Click on component to iterate. Click on iterInstMultiplier parameter -> Create Parameter Range" in ADE.

This is a great feature, and I wonder if and how one can evaluate "iterInstMultiplier" of the affected instance array in an Output Expression.

Assume I have an array of parallel transistors and I would like to calculate the current through each individual transistor, then one way is to record total current by an iprobe and then divide by "iterInstMultiplier" ascurrently set by parameter. (This is just a simple example, not the actual problem I am trying to scolve.)

But how to access the value of this parameter?

I found a rather complex work-around:

In CIW, i enter

openResults()

selectResults()

report()

and then I find the alias name "DPAR_1" that represents the parameter I am looking for. Then, using

pv("top-level" "DPAR_1" ?result "designParamVals")

I can finally access its value. However, if there is more than one such parameter, it starts getting complicated.

So, I guess there MUST be a much simpler way to do this directly?

Unable to post/reply with attachments in this forum anymore

dontpanic — Wed, 10 Jun 2026 13:29:35 GMT

Hi! Since a long time now I am repeatedly unable to post in this forum, specially when trying to add attachments (like simulation snapshots) to my posts, but also happens with just plain text and/or when trying to reply to other posts.

Specifically, I get an error window in the top-right area saying "An error has occurred. Try again or contact your administrator". Sometimes this is followed by another message saying that my post has been flagged as spam; sometimes there's no such message but after pressing the "Post" button the page just hangs and nothing happens.

Is anyone else experiencing this problems? Thanks in advance for any help!

Jorge.

How to force/specify which variable Assembler uses as "x-axis variable" for plotting?

AC202503109020 — Tue, 09 Jun 2026 15:38:59 GMT

Hello! I cannot figure out how to force/specify which variable Assembler uses as "x-axis variable" for plotting, when using corners for doing sweeps.

I have prepared the following "toy example" that describes well the problem. I have a maestro view which a single test that does a single-point DC simulation of an NMOS, and calculates the gm from the opPoint results. The gate, drain and bulk voltages of the NMOS are defined by the variables VG, VD and VB, respectively.

I also have 3 corners in my view:

"CornerA__fixed_VD" = a "single-point" corner with an explicit value for the VD variable (<---this models a single-point corner used in my real-life application for some sort of calibration condition)
"CornerB__sweep_VG" = a sweep of the variable vG (<--- this models an actual sweep of a parameter, as I would normally be interested in doing)
"CornerC__sweep_VG_at_explicit_VB" = a sweep of the variable vG too, but this time also with an explicit value for variable VB.

Here are 2 cases, with and without the problem:

Case #1: If I run corners A and B together, and use the "Plot all" option from the results, Assembler uses "VG" as the independent variable for plotting, and I get a nice trace for the results of the sweep.
Case #2: However, if I run corners A and C together, and plot as before, Assembler uses "VG" as the independent variable for plotting, and as a result I get a nonsensical plot with the results of the sweep scattered across several traces.

So, how can I force Assembler to plot w.r.t. the "swept" variable "VG" in Case #2, just as it does for Case #1?

Thanks, Adam.

Note1: Please note this is a toy example: I know there are other ways to do sweeps, but the one I describe here is representative of the actual situation I encounter in my real scenario.
Note2: I know about the "Swap Sweep Var" in VIVA, but unfortunately this doesn't solve my problem, as I would need to manually do this each time, which is not practical in my real scenario (Plotting Templates doesn't help either, they seem unable to work with traces created through the "Swap Sweep Var" method).

Monte Carlo simulations with a multi-process circuit

Darrell L — Tue, 09 Jun 2026 13:39:23 GMT

We are designing a module that will be made from two die bonded together to form a single device. Each die uses the same process, but come from different wafers. Some circuits will be split between the top and bottom die. I have used MTS options to cover corner cases between the two die, ie simulate the bottom circuits using an ss corner while the top circuit uses an ff corner. But I would like to simulate some circuits using Monte Carlo. It is not clear to me if the top die models and bottom die models will be treated independently, or if it will simulate both halves as if they are both on the same wafer. I want to see results where the process variation is completely independent between top and bottom, but the matching is still good between devices on the same half.

Can you tell me how to get Monte Carlo results that show me results when the process varies independently for two sections of the circuit hierarchy, and mismatch occurs between devices on the same half?

Thanks,

python version of cds_srr

AC202503109020 — Tue, 09 Jun 2026 12:34:36 GMT

I like to use the cds_srr tool from matlab to process psf data from our simulations.
Matlab requires an expensive license however and it is quite difficult to build easy-to-use command line tools for my users with it.
Is there a python equivalent tool which does similar things?

Guidance on reducing RLCK extraction size for PDN inductance analysis (Quantus PVS)

baltaci — Tue, 09 Jun 2026 07:31:47 GMT

Hello,

I am using IC 23.1-64b.43.

My goal is to estimate the series resistance (R) and series inductance (L), including mutual inductance, between the supply (VDD) and ground (VSS) pads and a digital core in a power integrity analysis of a digital circuit. I am primarily interested in the PDN impedance behavior between VDD and VSS.

To reduce parasitic extraction complexity and the size of the extracted view, I simplify the design by keeping only the top-level metal power distribution network (VDD and VSS) between the pads and on top of the digital block. I remove active devices and the digital core, since the internal core behavior (including decoupling capacitance) is already known and modeled separately.

I am currently using the PVS Quantus RLCK extraction flow. However, the resulting extracted netlist becomes very large (~2.5 GB), mainly due to inductive segmentation and dense mutual coupling terms. As a result, Spectre AC simulation fails due to swap/memory exhaustion.

Could you please advise:

Is there a way to reduce the size of the extracted RLCK netlist in Quantus PVS, by reducing the number of lumped elements generated during parasitic extraction (e.g., inductive segmentation and mutual coupling complexity), while still preserving sufficient accuracy for PDN AC behavior between VDD and VSS? In other words, is there a supported method to obtain a more compact or reduced-order lumped representation of the inductive network in order to reduce simulation memory requirements and prevent swap/memory exhaustion during Spectre analysis?
Outside of the standard Quantus PVS RLCK flow, is there an alternative Cadence-recommended approach or tool to achieve this objective more efficiently? My main goal is to obtain the AC impedance behavior of the PDN (VDD/VSS) from pads to the digital core, effectively capturing series resistance and inductance (including mutual coupling), but in a more computationally efficient or reduced-order form suitable for simulation.

Thank you.

Parameterization of Hidden Parameters

JT202409108313 — Tue, 09 Jun 2026 06:08:18 GMT

Is there a way to add to Assembler's parameter list those device parameters that may be hidden (AKA Display Condition is not blank/t)?

Constraint is that the Display Condition cannot be edited but the condition can be triggered once the device is used in a circuit.

I can trigger it to show, add it to parameter list, then trigger it to hide again and I think that would pose no problem when I sweep it. However, that would be much of a hassle if I will do it for all instances of the device on different subblocks. Is there a way to make it faster?

viva trace color palette: rectangular vs smith chart plot

TommasoF — Mon, 08 Jun 2026 20:06:32 GMT

Hello all,

when plotting a swept signal (e.g. S11 vs bias conditions) on a smith chart I get a different color palette between the rectangular and smith chart plot. How can we match them such to use the same palette?
thanks
Tommaso

Memory usage during simulation

dogman4 — Mon, 08 Jun 2026 09:45:58 GMT

Hi friends

I simulate the circuit with assembler in presim; the circuit is rather complex and is a boost circuit. I only selected to save around 1000 waveforms in total. The simulation runs with tran:conservative, and the high performance settings are :APS ; Error Preset: Moderate; Use ++aps selected; #threads:24(Sorry, an error occurred when I tried to upload the picture.)

Here is my issue: during simulation, I set three voltage states via global Variables within the same assembler and run three simulations simultaneously. The three simulations differ only in voltage settings. Everything works normally at the start of the simulation, and the VIRT and RES usage checked via the TOP command in the terminal are within normal ranges. However, as simulation time elapses — for instance, after four days of continuous simulation this time — the memory usage diverges drastically: 1st simulation: VIRT: 97.6g, RES: 97g. 2nd simulation: VIRT: 63.1g, RES: 62g. 3rd simulation: VIRT: 7000m, RES: 8.1g Moreover, VIRT and RES keep rising steadily as the simulation runs longer.

What configuration adjustments can I make to keep VIRT and RES within a normal range of several gigabytes?

very thanks in andvance

My virtuoso version: "@(#)$CDS: virtuoso version 6.1.8-64b 09/03/2024 19:11 (sjfhw316) $"

My spectre version: Version19.1.0.063 64bit--10 Aug 2019

bindkeys of library manager

dogman4 — Thu, 04 Jun 2026 04:41:02 GMT

Hi,friends

I want to change the default bindkeys Ctrl+O to Ctrl+E inside Library Manager. How can I do this?

My virtuoso version: @(#)$CDS: virtuoso version 6.1.8-64b 09/03/2024 19:11 (sjfhw316) $
My spectre version: Version19.1.0.063 64bit--10 Aug 2019