Custom IC Design - Recent Threads

Monte Carlo over design variable sweep in ADE XL

RA20250218276 — Wed, 08 Jul 2026 06:42:15 GMT

I am using virtuoso version 6.1.8

I am trying to do monte carlo simulation over a circuit. But to get the output, I need to sweep design variable.

Basically I need to sweep the design_variable and the output I intend to obtain is output(design_variable=1) - output(design_variable=0) and so on. I do this by creating an expression with EvalType("corners") so it is evaluated once after the sweep is complete.

I have also read several forum posts that says ADE XL Monte Carlo only supports measurement over corners, so I created 65 different corners each with different input.

Then I retrieve the output of each corner using leafValue(VT() "design_variable" ValueAtEachCorner) and use it as part of the output expression.

But when I do monte carlo on that, I get the plot of each output expression across mc_paramset instead of scalar value such as mean, stdev, max, min.

Technically, I can save the plot as csv and calculate mean, stdev, max, min and anything else I need. But are there other ways to do it? Perhaps using OCEAN script measurement?

Also, using leafValue() to retrieve the output of each corner does work, but are there better ways to get output result that needs design_variable sweep?

One schematic for multiple layouts

M202602061138 — Mon, 06 Jul 2026 14:19:49 GMT

What is the best way to handle multiple layouts of different aspect ratios using the same schematic when using LayoutXL?

We don't really want to duplicate the same schematic multiple times, but we do want layout XL to pass through the correct chosen aspect ratio and to maintain that layout when you do an update components and nets.

eg: circuit1 is used in 3 different locations with different shape/size areas available so requires 3 different layouts, layout_A, layout_B & layout_C

Would it be best to make it a pcell with Callback and CDF Parameters or use physConfig or another method?

Regards

Mike V.

RE: One schematic for multiple layouts

Kevin T Buck — Tue, 07 Jul 2026 20:37:49 GMT

I don't understand what the issue is here, you might need to be more specific. You can create multiple layout views within a cell and then using a physConfig view to specify the layout you want for each instance.

Stop the simulation after the GUI crash

dogman4 — Tue, 07 Jul 2026 04:40:32 GMT

Hi，friends

When running simulations with Assembler, the simulation session is interactive.1. I previously set `continueICRPRunOnAbruptGUIExit` to t. However, Virtuoso crashed before the interactive.1 simulation finished. After noticing issues with the partial results generated, I need to terminate the interactive.1 simulation.

How should I do this?

My virtuoso version: "@(#)$CDS: virtuoso version 6.1.8-64b 09/03/2024 19:11 (sjfhw316) $"
My spectre version: Version19.1.0.063 64bit--10 Aug 2019

Liberate for characterizing emerging transistor technology

CW202607067723 — Mon, 06 Jul 2026 18:58:47 GMT

Hi there,

I'm developing a PDK/library for an emerging transistor technology. I've developed and validated a level-61 spice model for the transistors (non-Si-based) and the model can run in Spectre. The next step is to build standard cells for logic gates, characterize them, and generate .lib timing/power models for use in digital design and system-level evaluation.

I'm new to Liberate and was wondering if it is the right tool for this task. In particular:

Can Liberate characterize custom transistor-level cells using Spectre with a Level-61 device model? My understanding is Liberate should not depend on the internal transistor technology of the cell. As long as the Level-61 model is supported by Spectre, and Liberate can invoke Spectre on the transistor-level netlists, Liberate should be able to characterize the cells. Is that correct?
Can I start with schematic-level/pre-layout netlists, and later move to PEX-extracted netlists?

Any guidance or pointers would be greatly appreciated. Many thanks!

All the best,
Kevin

ADE Explorer: How to pass a design variable to a parameter array and another design variable as a string parameter to an instance - Spectre vs. AMS

Volker T — Thu, 02 Jul 2026 10:26:53 GMT

Hi,

I am referring to the following two blog posts, both dealing with ADE Explorer and/or Spectre, as an introduction to a similar problem I have with ADE Explorer and AMS.

ADE Explorer and Spectre

1. How to Pass a String Design Parameter to a Cell

2. Defining Verilog-A vector in the maestro view

The first deals with the issue that when we have a parameterizable cell, like e.g. an instance "myInstance" of a cell using a Verilog-A view, that has a string parameter, e.g. "fname" that we want to specify by design variable, the Spectre netlist does not contain the value of the design variable, but its name only.

Example:

At the beginning of the Spectre netlist, we see the parameters passed to Spectre, e.g.

parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we only see

myInstance trise=trise tfall=trise tdelay=0 \
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile="fname"

So, instead of our string defined by design variable value, we only see the design variable name as a string passed to the instance's string parameter "logfile",

The solution shown by Andrew Beckett suggests to use SKILL functions to remove the respective string parameter while leaving the other string parameters in place:

almGetStringParameterList("mylib" "mycell" ?view "veriloga")

=> (fname someOtherParam somethingElse)

almSetStringParameterList("mylib" "mycell" '(someOtherParam somethingElse) ?view "veriloga")

=> (someOtherParam somethingElse)

The former function identifies all string parameters used by the respective view of a cell of a library (fname, someOtherParam and somethingElse in the example shown) and then the latter function can be used to set the same list minus the string parameter we would like to pass by design variable (e.g. fname) as the new string parameter list. That way, our Spectre netlist gets the value of the string parameter, and not only its name.

Now the beginning of the Spectre netlist still looks like this:

parameters temperature=27 vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

But later in the netlist, when we look at the instance "myInstance" that receives some of these parameters, one of which is the "fname" string parameter, we now see

myInstance trise=trise tfall=trise tdelay=0 \
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname

So, instead of "fname" (in quotes, hence being a string), we only see fname without quotes, hence referencing the respective Spectre parameter.

Problem solved, instance parameter "logfile" is now fed by Spectre parameter "fname" containing string value "/tmp/mylogfile.log" of design variable "fname"..

The second post deals with parameter arrays. Again, let's assume we use an instance of a cell using a Verilog-A view, that has a parameter array, like

parameter integer pattern[2:0] = {1, 2, 3};

and we would like to use a design variable "myPattern" for the definition of the pattern, in ADE, then we cannot just enter [4 5 6] for that design variable value to define a new pattern, as ADE interprets that as a literal or SKILL code.

Andrew Beckett shows the solution for this in the referenced post #2, namely to use strcat("[4 5 6]") as design variable value instead. This gives valid SKILL code for ADE, translates into string "[4 5 6]", which translates into Spectre parameter [4 5 6].

Example:

At the beginning of the Spectre netlist, the parameter list now is

parameters myPattern=[4 5 6] vdd50=5 fname="/tmp/mylogfile.log" \
debuglevel=1 tperiod=50n trise=100p tsdelay=10n

Later, when the respective instance occurs in the netlist, we see something like

myInstance trise=trise tfall=trise tdelay=0 pattern=myPattern\
tsdelay=tsdelay tperiod=tperiod vdd=vdd50 logfile=fname

So, similar to the string parameter described before, the instance parameter now gets assigned the correct Spectre parameter.

So far, so good, problems solved for ADE Explorer and Spectre.

ADE Explorer and AMS

Now let's use the same test bench, using the same cells and design parameters, but AMS as a simulator. As far as I know, AMS uses a different netlister (UNL?), and that apparently behaves differently.

The instance now gets its parameters assigned like this

myInstance #(.trise(cds_globals.trise), .pattern("myPattern") .tperiod(cds_globals.tperiod), .tsdelay(cds_globals.tsdelay), .vdd(cds_globals.vdd50), .tdelay(0), .tfall(cds_globals.trise), .logfile("fname"), .debuglevel(cds_globals.debuglevel)) I1 (.nrst( nreset ), .mclk( mclk ), ... );

There is no "pre-translation" of design variables into AMS parameters to be found as a list (but apparently there exists one, named "cds_globals", as one can see for the other parameters). But both the string parameter and the array parameter do not show up in cds_globals but are used directly as a string containing the design variable name instead of its value.

So the question is, is there any trick similar to the two shown for Spectre that we can create a netlist using design variable values instead of design variable names?

Efficient iterative methods for threshold extraction (ex: extraction of the input referred offset voltage of a clocked comparator or the calibration code of a bandgap etc.)

baltaci — Tue, 30 Jun 2026 08:30:13 GMT

Hi all,

I would like to ask whether there are recommended methodologies for efficiently extracting a threshold condition that is otherwise defined implicitly and would normally require fine parameter sweeps.

Two representative examples where this arises:

In a clocked regenerative comparator, the input-referred offset is defined as the differential input at which the system switches state. A brute-force sweep over the input requires increasingly fine resolution, and the number of simulations grows rapidly as the desired error tolerance is reduced.
In DC operating-point calibration problems such as bandgap temperature compensation code tuning, the target digital calibration word is typically found by iterating until a target operating point is reached (or by finding the minimum slope). A full sweep over all possible codes is inefficient, whereas a successive-approximation approach can converge in logarithmic time.

In both cases, the brute-force approach can be viewed as a linear (or effectively rapidly growing) search:

for each candidate value → run simulation → evaluate condition → continue sweep

where achieving higher accuracy directly translates into a large increase in simulation count.

Instead, a more efficient formulation would be an iterative search (such as SAR):

initialize upper and lower bounds
while error > tolerance:
- select midpoint
- run simulation
- update bounds based on result

which reduces the number of simulations from linear scaling to logarithmic scaling with respect to resolution.

Are such successive-approximation style extraction methods considered standard practice for this class of problems? In particular, are they supported or commonly used within verification flows (including GUI-driven environments such as Assembler), especially when Monte Carlo mismatch analysis is involved where each sample may require an inner convergence loop for each iteration?

Additionally, I would like to ask whether an Ocean scripting-based solution is typically used for implementing such iterative flows. If so, is there guidance or best practice on ensuring that such scripted approaches remain competitive in runtime compared to traditional sweep-based methods, especially when combined with Monte Carlo mismatch simulations?

Thanks in advance.

Can

RE: Efficient iterative methods for threshold extraction (ex: extraction of the input referred offset voltage of a clocked comparator or the calibration code of a bandgap etc.)

AVAQ Semi — Thu, 02 Jul 2026 07:35:40 GMT

A practical way to solve this is to treat the problem as a root-finding/search problem rather than a brute-force sweep.

For quantities such as comparator input-referred offset, bandgap trim code, LDO trim code, or any calibration parameter where the output changes monotonically with the search variable, a binary search (successive approximation) is usually the most efficient approach. Instead of sweeping hundreds or thousands of values, each simulation halves the remaining search range, so the number of iterations grows as log₂(N) rather than N. This provides a dramatic reduction in simulation time while maintaining the desired resolution.

In Cadence/Spectre, I've had good results implementing this using either:

SpectreMDL with looping/search statements.
SKILL/OCEAN scripts that automatically update the design variable after each simulation.
A small Verilog-A controller that performs the search internally, which is especially convenient for Monte Carlo characterization.

For clocked comparators, I also recommend combining the search algorithm with Monte Carlo mismatch so that each sample converges to its own offset voltage automatically, instead of performing a dense input sweep for every run. This is significantly faster than the traditional ramp-based method while producing essentially the same statistical results.

The key requirement is that the calibration variable has a monotonic relationship with the measured metric. If hysteresis or multiple stable operating points exist, the search algorithm should be modified accordingly (for example, by defining separate rising/falling thresholds or using a hysteresis-aware search strategy).

RE: Schematic generation form spice file

VIRAJ PANCHAL — Wed, 01 Jul 2026 07:15:39 GMT

Thanks for your suggestion,

Ya the error message I understood, so do I change viewTypeName as schematic in anywhere in skill or dB files..?

I have checked my spice file and library(it has writable permission); both are proper.

I have give the reference libraries analogLib, basic, sample and <maintechLib>( in this case it is "cds_ff_mpt"). And I think no need for device mapping file, it should work with device map file. (I already cross checked in cadence RAK).

I have attached my spi file as well as spiceIn log file. In spiceIn log file there is no information in last line. !! I thick it is incomplete.

Schematic generation form spice file

VIRAJ PANCHAL — Tue, 30 Jun 2026 14:11:27 GMT

Hi everyone,

I am trying to generate schematic from spice(.spi) file through import spice option in virtuoso. But during schematic generation process I faced below error massage.

*WARNING* (DB-270211): dbOpenCellViewByType: Cannot open cellview 'testLIB/DFCNQD1BWP6TSA16P96CPD/schematic' in 'a' mode because it does not exist or viewTypeName required to create a new cellview is not specified. Ensure that the cellview exists or to create a new cellview by specifying viewTypeName. Valid values for viewTypeName are "netlist", "schematic", "schematicSymbol" and "maskLayout".

According to above screenshot, The schematic view is not found in testLIB library. But how does it found before the schematic generation..!!?? It only give the netlist_tmp (blank schematic) as output but it should be schematic as output file.

Kindly anyone tell me what's the issue.!?

ERROR WHEN PRESS QUANTUS SETUP FORUM

RM202605273230 — Mon, 29 Jun 2026 17:33:45 GMT

Hello

for post layout simulation i wanted to extact layout netlist when i press quantus setup it shows *Error* eval: unbound variable - tabField in log box could you please help me to fix this error

Thank you

RE: ERROR WHEN PRESS QUANTUS SETUP FORUM

RM202605273230 — Wed, 01 Jul 2026 07:14:10 GMT

could you plese help me please when press quantus setup forum to set the extraction as spice file and rc that is not opening it shows *Error* eval: unbound variable - tabField

RE: Schematic generation form spice file

AVAQ Semi — Wed, 01 Jul 2026 06:38:25 GMT

The error message is actually a bit misleading. It is not saying that the schematic already exists and then disappears. It is saying that Virtuoso failed to create the schematic cellview.

DB-270211 is typically generated when dbOpenCellViewByType() is called without a valid viewTypeName while trying to create a new cellview. For a new schematic, the view type must be "schematic"; otherwise Virtuoso cannot create testLIB/<cell>/schematic and only temporary data (such as netlist_tmp) may be left behind. This is expected behavior when the import process aborts.

A few things I would check:

Verify that File → Import → Spice is configured to generate a schematic view rather than only a netlist.
Check the spiceIn.log file instead of only the CIW output. The first error in the log is usually the real cause.
Make sure your target library is writable and is an OA library.
If the netlist contains standard cells or custom devices, verify that the reference libraries and device mapping file are correctly specified. Missing mappings often cause the import to terminate before schematic generation completes.

RE: Parasitic extraction with StarRC

Phd SA88 — Tue, 30 Jun 2026 13:46:03 GMT

Thank you

Parasitic extraction with StarRC

Phd SA88 — Tue, 30 Jun 2026 11:05:00 GMT

Deal all,

I would lik to do parasitic extration with StarRC. Thus, when opening the StarRC Parasitic view genaration, i added correctly all paths, as seen below:

Furthermore, i edit correctly both of file .snp_settings and the starrcxt.cmd. However when i click on apply, there is an error:

ERROR: MAPPING_FILE /working_directory/est3/STAR/LVS/calibrestar.map cannot be found.

So, the svdb folder and the calibrestar.map are not created which ensure that LVS does not occured;

Please help me to resolve this problem and thank you in advance

Best Regards

RE: Parasitic extraction with StarRC

Andrew Beckett — Tue, 30 Jun 2026 11:10:05 GMT

StarRC (and the interface to it within Virtuoso) is a Synopsys tool, so you would be better off asking this question on one of their forums or to their customer support.

Kind Regards,

Andrew

Recommended methodology for PSRR characterization of a clocked regenerative comparator

baltaci — Mon, 29 Jun 2026 07:41:22 GMT

Hi all,

I am trying to characterize the PSRR of a clocked regenerative comparator (StrongARM-type latch), and I am struggling not only with the simulator setup itself but also with the definition of PSRR for a latched comparator.

For switched-cap amplifiers and other periodically time-varying but small-signal linear circuits, the usual SpectreRF flow (PSS followed by PAC/PXF) makes sense because the circuit can be linearized around its periodic operating point and the output is a continuous analog quantity.

A regenerative comparator seems fundamentally different. Around the decision point, the small-signal gain becomes extremely large, and the final output is binary (either 0 or VDD). A very small perturbation in the input or supply can completely change the final decision. Because of this, I am having difficulty understanding what an "output-referred PSRR" would even mean.

My concern is that a PSS+PXF flow may not provide a meaningful PSRR metric in this case, unless there is a specific methodology or interpretation that I am missing.

Intuitively, it seems that supply noise should manifest itself as one of the following:

An input-referred offset shift (equivalent input error due to supply variation),
A change in decision time,
A change in metastability probability or decision error rate.

So my questions are:

Can PSS/PAC/PXF be meaningfully applied to this type of circuit, and if so, how should the results be interpreted?
Is there a recommended Cadence/SpectreRF methodology for characterizing supply sensitivity of a clocked comparator?

I would appreciate any guidance or references on how others typically characterize PSRR or supply sensitivity for dynamic comparators.

Thanks in advance.

Can

noise summary missing after pnoise simulation

gangliurfic — Sun, 28 Jun 2026 05:26:31 GMT

Hi,

I run a PSS+Pnoise simulation and saved results. Usually after the simulation is done, I can Print-Noise Summary to show the contributions.

Right now after my simulation, when I do this, I get an error

ERROR (EXPLORER-2404): Cannot find a setup database entry for handle 0.
Provide a valid database handle and try again.

*Error* error: Cannot find a setup database entry for handle 0. - nil

Also, the noisesummary folder is missing in the results directory.

Any idea why this is happening?

I am using IC25.1 ISR4.

Thanks.

PEX Results Much Worse Than Schematic Simulation

AVAQ Semi — Thu, 25 Jun 2026 08:41:59 GMT

Hi everyone,

I am working on a low-noise analog amplifier in Virtuoso and recently completed the layout.

The schematic simulation results look good and meet the target specifications. However, after running parasitic extraction (PEX) and re-simulating the extracted view, I observed a much larger gain degradation than expected. The DC operating points remain almost unchanged, but the AC gain drops by around 20%.

I have already checked:

Device sizes and connections
LVS clean
No obvious extraction errors
Same simulation setup between schematic and extracted views

My understanding is that interconnect parasitics should introduce some degradation, but this amount seems excessive.

For those with experience in analog layout and PEX analysis:

1. What are the most common causes of unexpectedly large gain reduction after extraction?
2. How do you usually identify which parasitic components are contributing the most?
3. Are there recommended debugging techniques within Virtuoso or Spectre to isolate the dominant parasitic effects?

Any suggestions would be greatly appreciated.

Thanks.

Replacing DSPF sub-circuits with their functional view in the Hierarchical Editor for an AMS Mixed-Signal Simulation

Josch — Mon, 22 Jun 2026 09:23:32 GMT

Hello Everyone,

I'm trying to optimise our design flow by better utilizing AMS simulation capabilities to decrease our simulation times. We work with Analog-On-Top and have smaller digital blocks in our analog blocks (config, pattern generators, etc...). I figured out how to this with schematic simulation or hierarchical av_extraced views. In both cases the individual blocks are discovered by the Hierarchical Editor and I can select in which way I want to simulate them (functional, schematic or av_extracted).

However our main workflow is DSPF based and I cannot get it working in such a way, that the Hierarchical Editor can detect the sub-block hierarchy in the hierarchical DSPF file. When I switch the top level block to DSPF and reload, all sub-blocks in the tree list disappear. I tried reading in the DSPF directly from the Hierarchical Editor menu and loading it as a DSPF cell view. The DSPF is hierarchical and has all the sub-blocks I care about defined as sub-circuits. I am using Calibre v2024.4_27.13, Quantus 24.1.0-p089 and Virtuoso IC23.1-64b.ISR17.40.

Is the av_extracted AMS Hierarchical Editor flow with a DSPF possible at all? If it's doable what could be the problem? If not what would be the correct approach? I also saw the documentation about DSPF-in-the-Middle (DSPFIM). Should this be used with DSPFs instead of the Hierarchical Editor?

I've also tried looking into IDSPF, but it seems like a hierarchical extraction is not possible in that format.

Thank you very much for your support.

Best,
Josch

How to use 500 bit conversion analog to digital expression

RM202605273230 — Tue, 16 Jun 2026 14:25:06 GMT

Hello

I am trying to convert 500 bits from analog.to digital and use in expression in Adexl.bit its taking upto 149 only how to use 500 directly could you please let me know Thank you

RE: How to use 500 bit conversion analog to digital expression

RM202605273230 — Wed, 17 Jun 2026 15:09:51 GMT

Thank you for the information

RE: How to use 500 bit conversion analog to digital expression

Andrew Beckett — Wed, 17 Jun 2026 13:19:29 GMT

Interactively (at least using the latest IC25.1 version; I didn't go back and check your old version) it works interactively in ViVA creating the bus. However, the problem with generating an output expression in ADE for this is that the expression gets very long and unwieldy.

I suggest trying to use a combination of the SKILL code in this post: abDumpWaveformsToVCSV.il (this should be loaded from your .cdsinit), and also abA2Bus.il from here

In the ViVA calculator, in the function panel, use the "fx" button to navigate to the abA2DBus.il code and then you'll be able to use it from the calculator. Using an expression such as this should then work:

abA2DBus(VT("/op<499:0>") "center" ?vCenter 0.9

Andrew

RE: How to use 500 bit conversion analog to digital expression

RM202605273230 — Tue, 16 Jun 2026 15:57:35 GMT

Hi Andrew,

To clarify the steps and the environment I am using, here are the details of my setup:

Tool and Environment Tool: I am indeed using Virtuoso Analog Design Environment XL. IC Sub-version: I am running IC6.1.8-64b.
Selecting "Analog-to-Digital" and Setting the Range in the Virtuoso Visualization & Analysis XL waveform viewer. From the top menu, I navigate to Measurements -> Analog To Digital. This opens the Analog to Digital dialog box, where I select the signal VT("/OUT<499:0>") and attempt to configure the threshold and logic center values.
Manually Entering the Bits / Expression Limitation I am entering the expression directly into the Outputs Setup tab of the main ADE XL window. Under the Details column for the expr type, I am using the awvCreateBus function combined with awvAnalog2Digital to stitch the bits into a single bitstring bus: value(awvCreateBus("OUT_BITSTRING" list(awvAnalog2Digital(VT("/OUT<31>")... When I manually expand this list to include all bits for the larger bus (up to 500 bits), the ADE XL expression field automatically truncates the string, cutting it off after it reaches roughly 149 bits. Even with the proper conversion process selecting "Analog-to-Digital" and setting the range in that dialog, it still reduces to 149 bits.

Please let me know if there is a more efficient function or a preferred method to handle large bit-width bus conversions in this version without hitting expression character limits.

sorry for the early message confusion

RE: How to use 500 bit conversion analog to digital expression

Andrew Beckett — Tue, 16 Jun 2026 14:58:58 GMT

[quote userid="912117" url="~/cadence_technology_forums/f/custom-ic-design/66075/how-to-use-500-bit-conversion-analog-to-digital-expression/1408687"]In ADE XL, I selected the analog-to-digital conversion options and set the value range.[/quote]

Where are you selecting "the analog-to-digital conversion options and set the value range"? Are you actually using ADE XL (which is an end-of-life product) or ADE Explorer/Assembler?

Which IC sub-version are you using?

[quote userid="912117" url="~/cadence_technology_forums/f/custom-ic-design/66075/how-to-use-500-bit-conversion-analog-to-digital-expression/1408687"]even when I tried manually entering all 500 bits, ADE XL automatically limited the expression to only 149 bits[/quote]

Where did you "manually enter" all these bits?

I'm trying to work out exactly what you did, as it's (still) not clear.

Andrew