Custom IC Design

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Discussion

If-else statement in VerilogA- Designing a memory element

Category: Custom IC Design

By Nishtha Sharma

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updated over 9 years ago by Nishtha Sharma

3 replies • 2663 views
Discussion

EMIR Units

Category: Custom IC Design

By rafaelon

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updated over 9 years ago by Tom Volden

5 replies • 15149 views
Discussion

Static current calculation using Ocean script

Category: Custom IC Design

By saikatc

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updated over 9 years ago by saikatc

1 replies • 13231 views
Discussion

Trouble with ocean script for parametric analysis using ADE L

Category: Custom IC Design

By saikatc

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updated over 9 years ago by saikatc

11 replies • 17671 views
Discussion

Script Skill: copy layers in the layout view

Category: Custom IC Design

By tahm

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updated over 9 years ago by Andrew Beckett

3 replies • 15912 views
Discussion

How could I make my PV GUI communicate with Virtuoso through port so gds export has no issue

Category: Custom IC Design

By mctang

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updated over 9 years ago by mctang

4 replies • 14824 views
Discussion

Aging simulation fails in mode URI_mode: appendage

Category: Custom IC Design

By Amel

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updated over 9 years ago by Andrew Beckett

1 replies • 13732 views
Discussion

Cadence library and cell views

Category: Custom IC Design

By Pyroblast

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updated over 9 years ago by Andrew Beckett

3 replies • 18005 views
Discussion

How can I edit the purpose of Pcell'Layers

Category: Custom IC Design

By tahm

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updated over 9 years ago by Andrew Beckett

3 replies • 1611 views
Discussion

In WSP, how to align different layout instances tracks in top level

Category: Custom IC Design

By Ganesh 213

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updated over 9 years ago by Ganesh 213

2 replies • 15016 views
Discussion

QuickAlign "center" to "edge-center" deprecated in Layout 6.1.7?

Category: Custom IC Design

By dontpanic

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updated over 9 years ago by Andrew Beckett

8 replies • 10131 views
Discussion

ADE-XL: How to (efficiently) sweep parameters over a "Statistical Corner"

Category: Custom IC Design

By dontpanic

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updated over 9 years ago by dontpanic

2 replies • 2365 views
Discussion

IC6 constraining/placing matched transistors

Category: Custom IC Design

By stuso

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updated over 9 years ago by Andrew Beckett

12 replies • 6802 views
Discussion

Inconsistency between time and freq. domain results in pss plot

Category: Custom IC Design

By VLSIiitm

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updated over 9 years ago by VLSIiitm

1 replies • 14409 views
Discussion

ADE-XL "Saving History" very slow

Category: Custom IC Design

By Rob Gregoire

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updated over 9 years ago by Rob Gregoire

10 replies • 4140 views

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