Custom IC Design

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Discussion

How to setup monte-carlo run for variation analysis in virtuoso

Category: Custom IC Design

By supriyo1985
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updated over 1 year ago by Andrew Beckett

1 replies • 5041 views
Discussion

XNOR Gate Operation Issue in Cadence

Category: Custom IC Design

By Maria98
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updated over 1 year ago by Maria98

2 replies • 5546 views
Discussion

Format/Syntax for Writing Aged Model Files for Reliability Simulations

Category: Custom IC Design

By rahulsingh
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updated over 1 year ago by rahulsingh

6 replies • 2576 views
Discussion

[Solved] Cannot Direct Plot PAC Current (Even though it is saved in outputs!)

Category: Custom IC Design

By MahdiMohammadi
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updated over 1 year ago by MahdiMohammadi

2 replies • 5598 views
Discussion

How to pop-up Log file of ADEXL/ADE Explorer once simulation

Category: Custom IC Design

By Binhngo1210
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updated over 1 year ago by Binhngo1210

3 replies • 2361 views
Discussion

using different specs for Fresh and playback at the verifier

Category: Custom IC Design

By analog2
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updated over 1 year ago by Andrew Beckett

1 replies • 4766 views
Discussion

How to view the output noise curve generated by a certain device or subcircuit in noise simulation？

Category: Custom IC Design

By zuiying
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updated over 1 year ago by Andrew Beckett

4 replies • 5713 views
Discussion

Difference between PM frequency from stb and result fromcalculato？

Category: Custom IC Design

By zuiying
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updated over 1 year ago by zuiying

5 replies • 6015 views
Discussion

Modgen not working with multiplier in RAK examples

Category: Custom IC Design

By Lahsiv902
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updated over 1 year ago by Lahsiv902

1 replies • 4793 views
Discussion

How to measure current...

Category: Custom IC Design

By VIRAJ PANCHAL
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updated over 1 year ago by VIRAJ PANCHAL

8 replies • 9219 views
Discussion

sideband in PNOISE vs harmonic in PSS

Category: Custom IC Design

By StanleyChe
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updated over 1 year ago by StanleyChe

12 replies • 9605 views
Discussion

environment variable for "optimize single point run" in job policy netlisting

Category: Custom IC Design

By sjwprcker
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updated over 1 year ago by Andrew Beckett

1 replies • 1446 views
Discussion

ADE/maestro: Define sweep for variables elegantly like we can do for parameters

Category: Custom IC Design

By StephanWeber
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updated over 1 year ago by Andrew Beckett

1 replies • 1155 views
Discussion

How to remove label in layot

Category: Custom IC Design

By VIRAJ PANCHAL
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updated over 1 year ago by VIRAJ PANCHAL

2 replies • 5723 views
Discussion

Import several pwl signals through one file? (need an real example)

Category: Custom IC Design

By Chungtest
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started over 1 year ago

0 replies • 4296 views

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