Custom IC Design

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Discussion

small signal TF from a file as a gain element in schematic.

Category: Custom IC Design

By vamshiky

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updated over 11 years ago by Andrew Beckett

1 replies • 13280 views
Discussion

How can you create a global net in a Spectre netlist that does not end in !

Category: Custom IC Design

By FormerMember

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updated over 11 years ago by Andrew Beckett

5 replies • 5515 views
Discussion

From spectremdl to ultrasim : any cadence solution ?

Category: Custom IC Design

By samung

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updated over 11 years ago by samung

7 replies • 15111 views
Discussion

Generating ocean script in Linux terminal.

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by skillUser

3 replies • 14820 views
Discussion

parametric analysis of mosfet length and width

Category: Custom IC Design

By madhanmo

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started over 11 years ago

0 replies • 14020 views
Discussion

Memory instance : ULTRASIM simulator setting

Category: Custom IC Design

By samung

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started over 11 years ago

0 replies • 13205 views
Discussion

ADEXL parametric sweep does not work

Category: Custom IC Design

By sram8t

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updated over 11 years ago by Andrew Beckett

1 replies • 14725 views
Discussion

Extracted parameters do not match with the schematic.

Category: Custom IC Design

By jagadishdn

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updated over 11 years ago by jagadishdn

2 replies • 14157 views
Discussion

How to multiply a waveform with the x axis vector

Category: Custom IC Design

By milind0y

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updated over 11 years ago by milind0y

2 replies • 17335 views
Discussion

Layout Porting between Foundries

Category: Custom IC Design

By KKANDOTH

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updated over 11 years ago by theopaone

5 replies • 16506 views
Discussion

Link pin labels over hierarchy

Category: Custom IC Design

By Narasimhan90

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updated over 11 years ago by Andrew Beckett

3 replies • 14083 views
Discussion

Knowing associated TECH-FILE location

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by Andrew Beckett

3 replies • 18358 views
Discussion

Entering infoname and info (captab) analysis in ADE

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by Andrew Beckett

3 replies • 16757 views
Discussion

Processing cadence result data from psf folder

Category: Custom IC Design

By RFStuff

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updated over 11 years ago by Andrew Beckett

7 replies • 20900 views
Discussion

NC-Verilog netlister setttings to output single netlist (not hierarchy-ihnl/ based)

Category: Custom IC Design

By jagarcia85

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updated over 11 years ago by Andrew Beckett

3 replies • 15224 views

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