Custom IC Design

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Discussion

Some DRC errors regarding pwell

Category: Custom IC Design

By tester
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updated over 15 years ago by Quek

3 replies • 14295 views
Discussion

Problems with expressions in Monte Carlo

Category: Custom IC Design

By Karo
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updated over 15 years ago by Karo

6 replies • 14627 views
Discussion

Check in Spectre license automatically

Category: Custom IC Design

By archive
•
updated over 15 years ago by archive

2 replies • 15274 views
Discussion

how to run the simulaiton for 1 ns step interval ..?

Category: Custom IC Design

By Sunil Kumar K
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updated over 15 years ago by Sunil Kumar K

5 replies • 14258 views
Discussion

Text output on Cadence Composer

Category: Custom IC Design

By archive
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updated over 15 years ago by Andrew Beckett

4 replies • 13497 views
Discussion

creating a matrix of instances in verilog-A

Category: Custom IC Design

By rickrevolta
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updated over 15 years ago by Andrew Beckett

2 replies • 16378 views
Discussion

Pin names

Category: Custom IC Design

By StreamCX
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updated over 15 years ago by Andrew Beckett

7 replies • 10333 views
Discussion

LvsIgnore Properties

Category: Custom IC Design

By frogconsultant
•
updated over 15 years ago by frogconsultant

12 replies • 30439 views
Discussion

How to implement this equation in VerilogA

Category: Custom IC Design

By princemahmmod
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updated over 15 years ago by Andrew Beckett

4 replies • 15657 views
Discussion

Cadence 6 waveform error vpwl vsrc

Category: Custom IC Design

By StreamCX
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updated over 15 years ago by StreamCX

9 replies • 9032 views
Discussion

Output SPEF-file from QRC contains only top level ports

Category: Custom IC Design

By Slawa
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updated over 15 years ago by Quek

1 replies • 6100 views
Discussion

Off-Grid pins warning in abstract generation

Category: Custom IC Design

By affaq
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updated over 15 years ago by Alex Soyer

3 replies • 13810 views
Discussion

subciruit initiated top-level current probe

Category: Custom IC Design

By Kalimero
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updated over 15 years ago by Kalimero

5 replies • 16289 views
Discussion

cadence verilog ams environment setup question

Category: Custom IC Design

By Wing2
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updated over 15 years ago by EricCDN

1 replies • 18176 views
Discussion

How to short small resistor for lvs purpose

Category: Custom IC Design

By harleyMax
•
updated over 15 years ago by Andrew Beckett

7 replies • 19187 views

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