Good morning Cadence community:
At the moment I am working on creating and developing one digital design, but during the first simulations steps the following situation appear:
I tried simulating verilog code to traffic design, in nclaunch tool, and I got the following error message:
ncvlog: *E,EXPMPA (/rtl/traffic.v,1|1): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
Please, could someone have one suggestion about what i am doing wrong?
Thanks in advance