Digital Implementation - Recent Threads

Issue with Time-Based Power Analysis in Joules (Single Frame Only)

DS202606023124 — Tue, 02 Jun 2026 09:16:37 GMT

Hi all,

I'm using Joules for power analysis on a Genus-synthesized netlist and trying to perform time-based analysis from a VCD file. However, despite loading the stimulus with read_stimulus -frame_count 10, only a single frame (stim#1/frame#1) is created. When I run compute_power -mode time_based, Joules reports that the stimulus contains only one frame and automatically falls back to average analysis.

My flow is:

Load technology files
Read HDL and elaborate design
Apply SDC constraints
Write elab.db

For power analysis:

rtlstim2gate -init $ELAB_JDB -keep_libraries
read_netlist
read_sdc
read_stimulus -frame_count 10 -file dump.vcd
compute_power -mode time_based

I expected 10 separate frames to be generated from the VCD, but only one frame appears. Has anyone encountered this issue or knows if additional settings are required to preserve multiple stimulus frames for time-based power analysis?

Any help would be greatly appreciated.

Thanks,
Dario

Special Wires: Pieces of the net are not connected together.

MC202410167019 — Wed, 29 Apr 2026 05:54:57 GMT

Dear all,

I am trying to do PnR using Innovus and after floorplanning, pin placement and macro placement , i am doing power planning . with this i have stated the global nets VDD VSS, after that created the core ring, macro block ring , strips . Then I did the sroute . But when i check_connectivity -nets {VDD VSS} -type special, i am getting many many errors

check_connectivity -nets {VDD VSS} -type special -ignore_unconnected_pins -error 10000
VERIFY_CONNECTIVITY use new engine.

******** Start: VERIFY CONNECTIVITY ********
Start Time: Wed Apr 29 11:22:36 2026

Design Name: post_proc_core
Database Units: 2000
Design Boundary: (0.0000, 0.0000) (1400.0000, 1000.0200)
Error Limit = 10000; Warning Limit = 50
Check specified nets
*** Checking Net VDD
Net VDD: has special routes with opens, dangling Wire.
*** Checking Net VSS
Net VSS: has special routes with opens, dangling Wire.

Begin Summary
   1226 Problem(s) (IMPVFC-200): Special Wires: Pieces of the net are not connected together.
   3550 Problem(s) (IMPVFC-94): The net has dangling wire(s).
   4776 total info(s) created.
End Summary

Please help me in this regards, I tried same flow with no macros , and there i was not getting these errors. But with macros , the errors were coming with sroute between the macro channel

max_transition , set_input_transition constraint in sdc file

keerthana — Fri, 24 Apr 2026 09:33:44 GMT

How to set the max_transition and set_input_transition constraint in the sdc file w.r.t different pvt .

I have view_worst, view_typical and view_best in a design each binding to .lib of ss , tt and ff respectively. While binding these with their sdc files, How to decide the value of set_max_transition and set_input_transition ?

Issue while performing signoffTimeDesign in Innovus

VLSI lab IITB — Tue, 13 Jan 2026 11:23:54 GMT

Hello everyone,

I am facing an Issue while executing signoffTimeDesign in Innovus . Once I invoke innovus tool, and run the below commands it works fine.

But , after I source my design and then do signoffTimeDesign , I am getting the following error -

innovus 2> signoffTimeDesign

*info: Tempus executable from /vlsi/cad/cadence/SSV231/tools/bin

**ERROR: (IMPESO-521): Tempus executable '/vlsi/cad/cadence/SSV231/tools/bin/tempus' has the following issue 'did not start', so tool won't be able to run signoff timing analysis.

It will be really helpful if you can please help me in resolving the error.

RE: Issue while performing signoffTimeDesign in Innovus

VLSI lab IITB — Fri, 16 Jan 2026 11:28:38 GMT

Any idea to resolve the error will be really helpful.

innovus create offgrid viacuts

Alessadnro — Fri, 19 Dec 2025 10:39:50 GMT

when using innovus, it sometimes create viacuts that are offgrid

the vias themselves are on-grid but the metal around the vias is sometimes offgrid (e.g. it has 0.001um offgrid placements, while the vendor requires things be on 0.005um)

on a small design, they can be fixed by hand, but on a large design the number of issues explode easily in the thousands.

on a large design the set_verify_drc_mode innovus command is not an option, since it is much slower than other DRC checkers (and it often get stuck).

So I would like to do all that it is possible, to have innvous not making the offgrid errors in the first place

1) I think innovus is aware of the grid being 0.005um, as most of the shapes generated are on a 0.005um grid. But I am not 100% sure
Is there a command to set (or get) the grid spacing in innovus?

innovus seems to have a grid command, but I cannot find the usage in the manual nor in the various Cadence training
even the -help option is not helpful
(so I am not sure if it is indeed defining the grid)

innovus 5> grid -help
wrong # args: should be "grid option arg ?arg ...?"

2) alternatively, is there a an innovus command to "extend" (e.g. overlapping an additional piece of metal) the offgridshapes, so that they snap on grid?

thank you

ecoChangeCell

MA202509235119 — Tue, 23 Sep 2025 11:06:13 GMT

Hi, I’m new to using Innovus and I’m trying to rename a submodule called “abc” to a new submodule "abc2" with the same ports in a netlist. The structure looks like this: top/u_abc. I need to change the module name of “u_abc” from “abc” to “abc2”. I’m trying to use ecoChangeCell with “top” set as the top_cell, but I can’t proceed because “top/u_abc” isn’t identified as an instance (it’s in hinsts). Can anyone help me with this?

RE: ecoChangeCell

JD20251204503 — Mon, 15 Dec 2025 06:12:37 GMT

If you want change only hinst name use "changeInstName" is more easy

please refer to https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000nVAWEA2&pageName=ArticleContent (Cadence support)

RE: ecoChangeCell

KL202411246729 — Wed, 10 Dec 2025 09:23:23 GMT

changing in verilog is more faster right?

Power and Net Area Discrepancies in Joules When Analyzing PR Netlists Across Different Tool Versions

QJ202512045614 — Thu, 04 Dec 2025 11:46:55 GMT

Dear Cadence Community,

Recently, our company upgraded Joules from version 22.17 to 23.14. While performing power analysis on the final place-and-route (PR) netlist of a project, I noticed a significant difference in the area and power reports between these two versions.

In Joules 22.17, the area report includes a non-zero Net Area value, and the report clearly states:

Interconnect mode: global.

However, in Joules 23.14, that line no longer appears. Instead, the report shows:

Wireload mode: enclosed,

and—more critically—the Net Area is consistently reported as zero.

This change directly impacts power estimation: the total power reported by Joules 23.14 is noticeably lower than that from 22.17. Based on silicon measurements from the actual chip, the power estimate from Joules 22.17 aligns much more closely with real-world behavior.

Therefore, I would greatly appreciate your guidance:

Are there specific TCL commands or startup options in Joules 23.14 that can restore the net-area calculation behavior (e.g., re-enable global interconnect mode) to match that of version 22.17?

Our goal is to obtain a more accurate power estimate consistent with prior results and silicon validation.

Thank you very much for your time and support!

Best regards

Procedure in Innovus common UI to generate scripts for placement

nrk1 — Fri, 31 Oct 2025 04:33:30 GMT

In an older Innovus version (152), the following lines were executed before placement. pnrflow/ was generated in innovus using "writeFlowTemplate -directory pnrflow"

./pnrflow/SCRIPTS/gen_flow.tcl all
make init

In the new common UI, "writeFlowTemplate" is replaced by "write_flow_template" according to the manual (foundation flows guide). When I run "write_flow_template -directory scripts" it generates the folder scripts/ and scripts/flow with the following content. How do I proceed? Web search points to a script "scripts/run_flow.tcl" as the equivalent of gen_flow.tcl, but no such script is generated in my case. Basically I need to equivalent of "gen_flow.tcl" and "make init" mentioned above.

scripts> 291: ls
design_config.template eco_config.template flow.yaml_template innovus_config.template setup.yaml_template
dist.py* flow/ flow_config.template metric_config.yaml
scripts> 292: ls flow
common_flows.tcl common_steps.tcl innovus_steps.tcl

=====

Innovus version info:

Version: v21.18-s099_1, built Tue Jul 18 13:03:50 PDT 2023
Options: -stylus

=====

Thanks

Nagendra

Procedure in Innovus common UI to generate scripts for placement

NK202510274558 — Fri, 14 Nov 2025 13:32:48 GMT

(I posted this on "Digital Implementation" forum a couple of weeks ago. I noticed that only a couple of posts in the last six months on that forum have replies. Hence trying my luck here.)

In an older Innovus version (152), the following lines were executed before placement. pnrflow/ was generated in innovus using "writeFlowTemplate -directory pnrflow"

./pnrflow/SCRIPTS/gen_flow.tcl all
make init

=====

Innovus version info:

Version: v21.18-s099_1, built Tue Jul 18 13:03:50 PDT 2023
Options: -stylus

=====

Thanks

Nagendra

RE: "Undefined scan chain" error during Innovus `place`

Pascal — Wed, 12 Nov 2025 09:43:41 GMT

i am happy to help!

"Undefined scan chain" error during Innovus `place`

GS202507021424 — Thu, 16 Oct 2025 15:58:29 GMT

I'm trying to run a RocketChip (rv64gc) design through the Genus/Innovus synth+place&route flow (with gpdk045 as the underlying technology), and running into a "scan chain" related issue during Innovus place (and subsequently cts). During place, I get this error:

    [check_scan_connected]: number of scan connected with
        missing definition = 5267, number of scan = 18274,
        number of sequential = 27937, percentage of missing
        scan cell = 18.85% (5267 / 27937)
    **ERROR: (IMPSP-9099): Scan chains exist in this design
        but are not defined for 18.85% flops. Placement and
        timing QoR can be severely impacted in this case!
    It is highly recommend to define scan chains either through
        input scan def (preferred) or specifyScanChain.

If I ignore this and continue by running cts, I then get this error:

    **ERROR: (IMPCCOPT-1349): Clock tree clock connects to 5 module(s)
        without definitions in the netlist.
    ...
    **ERROR: (IMPCCOPT-2196): Cannot run ccopt_design because
        the command prerequisites were not met. Review the previous
        error messages for more details about the failure.

Synthesis (with Genus) completes error-free, for whatever that's worth...

I suspect that this is somehow related to the RocketChip's debug interface, which has its own independent debug_clock and a few additional *reset signals:

    module ExampleRocketSystem(
      input         clock,
      input         reset,
      input         resetctrl_hartIsInReset_0,

      // debug interface:
      input         debug_clock,
      input         debug_reset,
      output        debug_clockeddmi_dmi_req_ready,
      input         debug_clockeddmi_dmi_req_valid,
      input  [6:0]  debug_clockeddmi_dmi_req_bits_addr,
      input  [31:0] debug_clockeddmi_dmi_req_bits_data,
      input  [1:0]  debug_clockeddmi_dmi_req_bits_op,
      input         debug_clockeddmi_dmi_resp_ready,
      output        debug_clockeddmi_dmi_resp_valid,
      output [31:0] debug_clockeddmi_dmi_resp_bits_data,
      output [1:0]  debug_clockeddmi_dmi_resp_bits_resp,
      input         debug_clockeddmi_dmiClock,
      input         debug_clockeddmi_dmiReset,
      output        debug_ndreset,
      output        debug_dmactive,
      input         debug_dmactiveAck,

      // mem_axi4_0 64-bit data width AXI (master) port;

      // mmio_axi4_0 64-bit data width AXI (master) port;

      // l2_frontend_bus_axi4_0_axi4_0 64-bit data width AXI (slave) port;

      input  [7:0]  interrupts
    );
      ...
    endmodule

In the .sdc file for Genus (synthesis), I have designated clock as the clock signal (using create clock -name "clock" -period ...), but I'm unsure of whether (and how) to deal with the debug_clock signal, or if that's even the way to address the subsequent "scan chain" errors I get during place...

Any clues, tips, or pointers much appreciated!

RE: "Undefined scan chain" error during Innovus `place`

GS202507021424 — Tue, 11 Nov 2025 18:46:50 GMT

Hi Pascal,

Many thanks, that did it!!!

I guess I need to remember GENUS*/doc/genus_attref/genus_attref.pdf for future reference, as a place to look for in cases where I feel "there ought to be a flag that does this" :)

RE: "Undefined scan chain" error during Innovus `place`

Pascal — Mon, 10 Nov 2025 19:51:16 GMT

Try putting thic command "set_db / .use_scan_seqs_for_non_dft" false in genus after elaboration and befor syn_gen

RE: "Undefined scan chain" error during Innovus `place`

GS202507021424 — Thu, 23 Oct 2025 18:07:08 GMT

I've also tried this with a very simple (8bit GCD) example with giolib045 pads -- absolutely no *deliberate* scan chains in that design!

During `place`, I get IMPSP-9099.

I tried working around it based on this older post: ERROR: (IMPSP-9099): Scan chains exist in this design but are not defined for xx% flops

Using ` setPlaceMode -place_design_floorplan_mode true` (in pre_place.tcs) fails with IMPSP-9537 -- says I should "use place_design" instead, not sure how I'd force it to do that...

Using `setPlaceMode -place_global_ignore_scan false` does *not* get rid of IMPSP-9099.

Ignoring these errors (by exiting from the tcl prompt I'm thrown into) then subsequently causes me to run into `cts` errors: (IMPCCOPT-2028): Too many clock instances are unplaced in the clock tree for CCOpt to continue.

Is there a standard way to prevent Innovus from wrongly assuming the existance of scan chains?

Thanks!

Skewing of sink pins at post route

PN202510149547 — Tue, 14 Oct 2025 14:26:18 GMT

Hi ,

In my design, the clock tree looks good up to the routing stage, and I want the tool to preserve it as-is. However, during the post-route optimization phase using:

opt_design -post_route -report_dir reports -report_prefix postroute -setup -hold

I noticed that the tool inserts a significant number of USKC cells, which disrupts the clock path and introduces considerable skew, leading to numerous hold violations. My intention is to prevent the tool from modifying the clock tree or altering the skew at sink pins.

I attempted to preserve the clock tree after CTS by applying the following constraint:

set_db skew_group:<skew_group_name> .cts_skew_group_constrains all

Unfortunately, this approach didn’t work, and the post-route stage still modified the existing clock tree.

".tch" file for QRC extraction of RC corners in MMMC.VIEW file.

GS202509267745 — Fri, 26 Sep 2025 11:43:09 GMT

Greetings of the day !

I have designed an SPI ( Serial Peripheral Interface) Module using TSMC65nm technology in Cadence Innovus. At last during the Sign-Off stage I am checking for Slack values (WNS/TNS) by clicking on the timing report. After the execution of this I'm getting an error saying "Extraction failed because *Quantus QRC* is not specified for all RC corners in MMMC file, this is mandatory for medium or high or signoff effortLevel postRoute extraction. If all files are unavailable, set 'setExtractRCMode -effortLevel low'. Ideally specify the technology file for each RC corner using the -qx_tech_file option of the create_rc_corner or update_rc_corner commands."

This error actually is due to the missing referencing to the ".tch" file in *MMMC.VIEW* " file, which is being loaded during design import in Innovus. I have searched for this .tch file everywhere in the TSMC 65nm technology bundle, but could not find it. However, for gpdks this .tch file is clearly available.

Kindly help me in knowing where this .tch file is accessed from for tsmc65nm technology or is it specified with some other name in the technology folder.

Thanks & regards,

Dr. Garima Shukla.

Hi, How virtual clock latency is getting updated after Clock tree synthesis stage and what parameters does it consider to update that latency?

MS202509109551 — Thu, 11 Sep 2025 02:28:46 GMT

How to create tech file (.tch) and captable file (.capTl) if we have .ict files from foundry

Keththura — Tue, 09 Sep 2025 20:25:16 GMT

I am trying to learn the implementation of a Digital design. I am following Cadence-RLT-to-GDSII course. But I am using my own pdk which is TSMC 65nm.
I am unable to file the Tech files and Captable files. I found in this forum that we can generate tech file from .ict files using Techgen.
But unfortunately, I don't know how to generate it. Can someone help me on this.

I really appreciate your help on this matter.

Thanks & regards,
Keththura

Timing Differences seen between Innovus & Tempus

AD20250812946 — Mon, 08 Sep 2025 03:27:28 GMT

Hi Experts ,

I see the following timing differences between Tempus & Innovus .

The path which is matching in Innovus but failing in Tempus .

Pasting the headers of both the reports :

Tempus : Failing

Path 1: VIOLATED (-0.0222 ns) Hold Check with Pin regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/CK->D

View: mission_Pff_ff_V0990_T125_Xrcmax_Fsvt35_clock_hold_T0_rcmax

Group: jtag_tck

Startpoint: (R) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_shift_reg_s_reg[0]/CK

Clock: (R) jtag_tck

Endpoint: (F) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/D

Clock: (R) jtag_tck

N-Sigma: 4.5000

Capture Launch

Clock Edge:+ 0.0000 0.0000

Src Latency:+ 0.0196 ( 0.0196, 0.000) 0.0079 (0.0079, 0.000)

Net Latency:+ 0.3363 ( 0.3298, 0.001) (P) 0.2755 (0.2813, 0.001) (P)

Arrival:= 0.3559 ( 0.3494, 0.001) 0.2834 (0.2892, 0.001)

Hold:+ 0.0284 ( 0.0201, 0.002)

Uncertainty:+ 0.1400

Cppr Adjust:- 0.0392 ( 0.0323, 0.002)

Required Time:= 0.4852 ( 0.4773, 0.002)

Launch Clock:= 0.2834 ( 0.2892, 0.001)

Data Path:+ 0.1685 ( 0.1856, 0.004)

Slack:= -0.0222 (-0.0025, 0.004)

Path 1: VIOLATED (-0.0222 ns) Hold Check with Pin regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/CK->D
View: mission_Pff_ff_V0990_T125_Xrcmax_Fsvt35_clock_hold_T0_rcmax
Group: jtag_tck
Startpoint: (R) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_shift_reg_s_reg[0]/CK
Clock: (R) jtag_tck
Endpoint: (F) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/D
Clock: (R) jtag_tck
N-Sigma: 4.5000

Capture Launch
Clock Edge:+ 0.0000 0.0000
Src Latency:+ 0.0196 ( 0.0196, 0.000) 0.0079 (0.0079, 0.000)
Net Latency:+ 0.3363 ( 0.3298, 0.001) (P) 0.2755 (0.2813, 0.001) (P)
Arrival:= 0.3559 ( 0.3494, 0.001) 0.2834 (0.2892, 0.001)

Hold:+ 0.0284 ( 0.0201, 0.002)
Uncertainty:+ 0.1400
Cppr Adjust:- 0.0392 ( 0.0323, 0.002)
Required Time:= 0.4852 ( 0.4773, 0.002)
Launch Clock:= 0.2834 ( 0.2892, 0.001)
Data Path:+ 0.1685 ( 0.1856, 0.004)
Slack:= -0.0222 (-0.0025, 0.004)

Innovus : Meeting

Path 1: MET (0.027 ns) Hold Check with Pin regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/CK->D
View: mission_Pff_ff_V0990_T125_Xrcmax_Fsvt35_clock_hold_T0
Group: REG2REG
Startpoint: (R) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_shift_reg_s_reg[0]/CK
Clock: (R) jtag_tck
Endpoint: (F) regif/tc_platform_n22ullph_extended_reg_inst_jtag_data_reg_i_dout_shadow_s_reg[0]/D
Clock: (R) jtag_tck
N-Sigma: 4.500

Capture Launch
Clock Edge:+ 0.000 0.000
Src Latency:+ 0.187 (0.187, 0.000) 0.187 (0.187, 0.000)
Net Latency:+ 0.382 (0.373, 0.002) (P) 0.339 (0.346, 0.001) (P)
Arrival:= 0.569 (0.560, 0.002) 0.526 (0.533, 0.001)

Hold:+ 0.029 (0.019, 0.002)
Uncertainty:+ 0.140
Cppr Adjust:- 0.025 (0.016, 0.002)
Required Time:= 0.714 (0.704, 0.002)
Launch Clock:= 0.526 (0.533, 0.001)
Data Path:+ 0.201 (0.223, 0.005)
Slack:= 0.027 (0.052, 0.006)

I see a huge difference between clock latencies in both the reports.

Any comment/ Suggestions .

My timing is badly failing in Tempus .

Thanks

addRing creating rings outside design boundary

TA202503121730 — Sat, 30 Aug 2025 03:41:26 GMT

It seems that there is a glitch involved with creating the power ring.I set the floorplan with floorPlan -d $TOP_macro_sizex $TOP_macro_sizey 0.612 0.612 0.612 0.612 -noSnapToGridThis sets the core and IO boundary properly and I can see the accurate measurements in the GUI.However, when I create the power ring using addRing -nets {VDD VSS} -type core_rings -follow core \
-center 0 -layer {top M8 bottom M8 right M9 left M9} -width 0.04 -spacing 0.04I receive this error,**WARN: (IMPPP-220): The power planner does not create core rings outside the design boundary. Check the design boundary, or specify valid offsets.
**WARN: (IMPPP-4051): Failed to add rings, because the IO cells might contain gaps. Run the 'addIoFiller' command to fill gaps between the cells and try again.When I change the -follow flag to io , Innovus creates a ring that is 1.0um away from the core boundary on all sides.

gsclib045 data sheet available?

FG202508072745 — Mon, 18 Aug 2025 14:37:26 GMT

While we were able to obtain all the required implementation views and reference manual for the gsclib045 example stdcell library, I was unable to find a data sheet that explains the individual cells. Specifically, I'd like to know about the syntax of the various flip flop types - e.g., a SDFFRHQX1 is probably a Scannable D-FF with Reset, but what does the (H)Q suffix mean? I could not find an explanation of this anywhere.

Any help is greatly appreciated.

Issue about using SkyWater130 and Genus

SR202412023415 — Fri, 08 Aug 2025 22:07:39 GMT

Hey all,

I am trying to synthesize a design using Cadence Genus with SkyWater 130. Although the synthesis does not report any issue, when I try to simulate the gate-level netlist using XCELIUM, it gives me all X's for all the signals.

I appreciate your help in advance for any insights.

Best regards