i am doing a project on synchronous fifo design using
verilog. below written is my coding. after simulation the waveform is
showing error regarding its not giving value of rdata_valid and is
showing a red line in waveform and due to it address is also not being
taken.i have attached the waveform also. the logic for write logic is
also not accepting the address(no change occurs while changing value of
read_ptr). i have attached my file with it so plz refer to it.
plz help me out in this. your guidance and solns will help me in completing my project work.
thank you so much sir for your time and i appreciate your suggestion and will surely work upon it. i will surely contact you again in future if i feel that m not able to find a solution to my problem.