Functional Verification Shared Code Forums

How to verify the functionality of synthesized netlist ?

Tejal Pawar
17 days ago

I am using SCL PDK for my design. I have written a verilog code and through synthesis obtained a sythesized netlist. So to verify the functionality of synthesized netlist in nc launch I used this netlist.v file along with standard cells verilog.v file and verilog_udp.v file but I am getting an error as follows:

|
ncvlog: *E,UDPROW (/home//netlist_simulation/stdlib_scl_pdk_ss_udp.v,12876|32): conflicting row output values row 11 and row 12.
? 0 ? ? 1 1 ? : ? : 0;

Please help  me!

Thanks,

Tejal Pawar

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