Functional Verification Shared Code - Recent Threads

e-code: Shareware RAM

snaptube — Thu, 20 Apr 2023 02:17:26 GMT

Modified version of shr_ram from erm_lib to support mvl_values
regards: snaptube

How to transfer trained an artificial neural network to Verilog-A

CJL — Mon, 17 Oct 2022 11:58:59 GMT

Hi all, I've trained a device model with the approach of an artificial neural network, and it shows well fit.

May I know how to transfer the trained model to Verilog-A, so that, we can use this model to do circuit simulation?

And I've searched for some lectures that provide the Verilog-A code in the appendix, but I'm freshman in the field of Verilog-A,

could anyone tell me each statement? such as

real hlayer-w[0:(NI*NNHL)-1

e-code: Shareware RAM

archive — Sun, 05 Feb 2006 00:28:51 GMT

Modified version of shr_ram from erm_lib to support mvl_values

Author: Hari Tirumalai, CMR Design Automation updated 4/12/2005

2843 bytes

Originally posted in cdnusers.org by Administrator

RE: help for $sscanf

Ahiad — Sun, 30 Aug 2020 05:51:52 GMT

try this $sscanf(line,"*%s *%s *%s * %s%s",string_arg);

help for $sscanf

jaichandra — Fri, 22 Apr 2016 04:03:22 GMT

Can anyone tell me how i can supress few strings or integers while reading with $sscanf.

I read a line from a file into a string. there are few strings and integers seperated by white spaces in the line. I am interested in one string which comes at postion 5 in the line. how can i suppress all other strings and integers with $scanf.

i tried the following syntax but it dint work.

$sscanf(line,"* * * * %s",string_arg);

i am tring to supress first 4 integers/strings in the line.

Creating cover items for sparse values/queue or define in specman

rgarcia071 — Fri, 12 Jul 2019 17:51:31 GMT

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

data :uint(bits:16);
opcode :uint(bits:16);
!valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
event data_e;
event opcode_e;

cover data_e is {
item data using radix = HEX, ranges = {
//I dont want to write all of this
range([0], "My range1");
range([10], "My range2");
//... many values in between
range([700], "My rangen");
};

item opcode;

cross data, opcode;
};

post_generate() is also {
emit data_e;
};
};

RE: Creating cover items for sparse values/queue or define in specman

rgarcia071 — Mon, 15 Jul 2019 15:51:51 GMT

Thank you very much Tudor, i was expecting specman to have something similar to 1800-2012 SV to define buckets using a list, I'll give it a try to the computed macro

RE: Creating cover items for sparse values/queue or define in specman

Tudor Timi — Mon, 15 Jul 2019 15:31:23 GMT

The ranges you pass to the ranges option have to by listed manually. There's no way of passing a list of range or something like that. Also note that the values used in the range have to either be literals or global scope variables that are set by the end of the setup phase.

The only way I can see at the moment is to use a define as computed macro.

RE: Using the Forum

jessejames — Tue, 07 May 2019 22:16:50 GMT

I am new at using OrCAD and i am getting this error when i try to import a gerber file into PCB capture. I am getting an "art_param.txt" in the search path.

please advise,,

Using the Forum

archive — Fri, 20 Jan 2006 18:23:10 GMT

Welcome to the Verification Shared Code forum, where you can attach e programs to help other users in using Verification products. For the benefit of others please include a brief summary of benefits of your e program.

This forum is not intended to be a substitute for Cadence customer support and/or documentation, but we do believe that it will be helpful and a way to tap into vast knowledge that exists in our user community. Of course, any software support, documentation and installation issues should also be directed to your preferred Cadence support channels.

File attachments must use one of the following file extensions:.doc, .pdf, .html .zip, .il,.jpg,and .gif. Size limit on the attachments is 750KB. If you have questions or need help with attachments, send an email to community_moderator@cndusers.org. We are able to increase the file size restriction on a case by case basis.

Administrator, cdnusers.org

Originally posted in cdnusers.org by Moderator

Specman Mode for Emacs

hannes — Tue, 11 Feb 2014 13:16:39 GMT

Attached is the latest emacs mode for e/Specman - version 1.23

Please follow the install instructions in the top section of the actual file
(after unzipping it) to install/load this package with your emacs.

RE: Specman Mode for Emacs

hannes — Wed, 12 Dec 2018 10:48:02 GMT

Hi,
once you unpack the tar file, have a look at the header area. There is an install section, which explains how to load this package.

RE: Specman Mode for Emacs

muzicarski — Wed, 12 Dec 2018 10:43:20 GMT

Thank You very much for this!

I found this through Your post on a blog, titled "e Language Editing with Emacs". May I suggest that You provide a link to a web page with instructions on how to manually install packages in Your original post? I had trouble with this issue, and I believe that more people will, so a simple guideline like a link could be very helpful! i.e. Like this one: http://ergoemacs.org/emacs/emacs_installing_packages.html .

Once again, thank You very much, You saved my day!

RE: Specman Mode for Emacs

thanik60 — Wed, 03 Oct 2018 09:34:00 GMT

ขอบคุณมากครับสำหรับความรู้ เป็นประโยชน์ มากๆ เลย ufabet http://www.ufa007.com/ufabet:AO

RE: vr_ad and AXI eVC integration

cmarqu42 — Wed, 19 Jul 2017 15:19:12 GMT

The code piece

                for i from 0 to size {
                    result.add(0x0);
                };

seems to be wrong/superfluous.

At least in my case, it made the read_reg macro return twice the expected data (with zeroes in the extra bytes), and only those zeroes were then taken (and the actual data stripped off).

vr_ad and AXI eVC integration

archive — Wed, 29 Mar 2006 12:30:57 GMT

Hi,

Attached is a file implementing the integration between vr_ad (the register and memory management shareware) and Cadence's AXI eVC. This is a working draft that can be adapted to your own environment. It was developed by Olivier Schuler from STMicroelectronics (many thanks!) and brought to us by Cadence's Patrick Oury.

Regards,
Avi

Originally posted in cdnusers.org by abehar

vr_ad register definition utility

StephenH — Tue, 13 Jan 2009 06:55:41 GMT

Hi All.

I put together a small Perl script to generate vr_ad register definitions from SPIRIT (IP-XACT) XML.
If you've got not idea what IP-XACT is, have a look here www.spiritconsortium.org/, then start pestering your design manager to use it :-)

The script can filter out registers and override R/W access types if needed.

An example XML file is included with the package so that you can play with it, and there's a detailed README.txt as well.

Here's an example of the generated e code:

// Automatically generated from xdmac.xml
// DO NOT EDIT, or your changes may be lost
<'

import vr_ad/e/vr_ad_top;

// Component = XDMAC
// memoryMap = xdmac
extend vr_ad_map_kind : [XDMAC];

// addressBlock = dma_eth
extend vr_ad_reg_file_kind : [DMA_ETH];

extend DMA_ETH vr_ad_reg_file {
  keep size == 20;
  keep addressing_width_in_bytes == 4;
};

// Register = command
// Reset    = 0x00
reg_def COMMAND DMA_ETH 0x0 {
  // Field resv3 = command[31:29]
  reg_fld resv3 : uint(bits:3) : R : 0 : cov ;
  // Field transfer_size = command[28:19]
  reg_fld transfer_size : uint(bits:10) : RW : 0 : cov ;
  // Field dma_transfer_target = command[18:14]
  reg_fld dma_transfer_target : uint(bits:5) : RW : 0 : cov ;
  // Field resv2 = command[13:10]
  reg_fld resv2 : uint(bits:4) : R : 0 : cov ;
  // Field transmit_receive = command[9:9]
  reg_fld transmit_receive : uint(bits:1) : RW : 0 : cov ;
  // Field resv1 = command[8:5]
  reg_fld resv1 : uint(bits:4) : R : 0 : cov ;
  // Field dest_address_enable = command[4:4]
  reg_fld dest_address_enable : uint(bits:1) : RW : 0 : cov ;
  // Field source_address_enable = command[3:3]
  reg_fld source_address_enable : uint(bits:1) : RW : 0 : cov ;
  // Field word_size = command[2:0]
  reg_fld word_size : uint(bits:3) : R : 0 : cov ;
};

// Register = queue_exec
// Reset    = 0x00
reg_def QUEUE_EXEC DMA_ETH 0x10 {
  // Field resv = queue_exec[31:1]
  reg_fld resv : uint(bits:31) : R : 0 : cov ;
  // Field exec = queue_exec[0:0]
  reg_fld exec : uint(bits:1) : RW : 0 : cov ;
};

extend XDMAC vr_ad_map {
  dma_eth : DMA_ETH vr_ad_reg_file;

  post_generate() is also {
    add_with_offset(0x00, dma_eth);
    dma_eth.reset();
  };
}
'>

Any comments, please feed them back to me so I can enhance the script.
Note that this forum forces me to post a .zip file rather than .tgz, please be careful to unpack the file under Linux, not Windows, else the DOS linefeeds will corrupt the Perl and XML files.

Steve

RE: vr_ad register definition utility

Lorean — Mon, 19 Sep 2016 22:15:30 GMT

Thanks! this was usefull for me too. Im working hard on something that envolves all that you explained. It was costing me alot of time and effort... so thanks !!!

RE: Hold violation at post P&R simulation

DESIGNARCHITEC — Mon, 01 Feb 2016 01:51:31 GMT

Hey, Until now the design is communication internally and hence the timing was good, but once IO pads have been placed the data coming from outside block should communicate with your block pin or from block pin to a std cell in your design, that means a delay may arise in this scenario. So try using IO buffers or create some feed-through ports to your design so that data may communicate effectively. Hope this may give some idea.

Hold violation at post P&R simulation

shahein — Mon, 08 Oct 2012 04:28:27 GMT

Hello,

I am working in a digital design. The functional, post synthesis and post P&R without IO pads are all working fine, i.e., functionally and with clean timing reports "no setup/hold violations". I just added the IO pads to the same design, I had to change the timing constraints a bit for the synthesis but I have a clean design at SOC Encounter, i.e., clean DRC and clean timing reports "no setup/hold violations". However, when I perform simulation using the exported net-list from SOC Encounter together with SDF exported from the same tool, I got a lot of hold violations. Consequently, the design is not funcitioning.

Why and how I can overcome or trobleshoot this issue?

In waiting for your feedback and comments.

Regards.

RE: vr_ad register definition utility

vgurpreet — Thu, 07 Jan 2016 07:57:47 GMT

Useful code.This is very helpful for me. Thank you. http://amansharma.in

RE: Specman Mode for Emacs

krawi992 — Tue, 14 Apr 2015 10:10:08 GMT

Thanks!

Re: Specman Mode for Emacs

Martin Garcia — Mon, 22 Sep 2014 06:17:10 GMT

[quote user="Martin Garcia"]

This is also very useful for me, I was looking for.

Penalista

[/quote]

Re: Specman Mode for Emacs

Martin Garcia — Mon, 22 Sep 2014 06:04:59 GMT

This is also very useful for me, I was looking for.