while trying to transfer a working mixed-signal system model from Mentor Graphics SystemVision to Cadence Virtuoso/AMSDesigner I came across the following problem.
Some of the VHDL-AMS components in my system model include generic parameters of type "time", for example:
entity comparator_d is generic ( delay : time := 1.0 us; hysteresis : voltage := 0.0 ); port ( terminal in_pos : electrical; terminal in_neg : electrical; signal output : out std_logic := '1' );end comparator_d;
I let Virtuoso (v6.1.8) create a schematic symbol from this code, then I instantiated the symbol on a new schematic with all generics left at their default values. When I netlist the design in ADE with the simulator set to "ams", the following netlist entry is created:
comparator_d #(.delay("1.0 us")) I10 (.\output ( net1 ), .in_pos( net2 ), .in_neg( net3 ));
The time value 1.0 us is passed as a string, which is not recognized as a valid time specification by the simulator.
Warning from spectre in `classd_models__shell_model__schematic__0x10000001':`shell_model', during hierarchy flattening. WARNING (SFE-30): "/home/hennig/sim/classd/shell_model/ams/config/netlist/netlist.vams" 28: shell_model.I10: `DELAY' is not a valid parameter for an instance of `CLASSD_MODELS__comparator_d__behavioral__0x10000001'. Ignored.
If I change the CDF parameters of the delay property so that the value is parsed as a number, I can change the netlist entry into something like this, ....
comparator_d #(.delay(1.0e-6)) I10 (.\output ( net1 ), .in_pos( net2 ), .in_neg( net3 ));
..., but then the simulator complains about a type mismatch.
Do you have any suggestions how to pass generics of type "time" correctly through a Verilog netlist to a VHDL-AMS component?