Functional Verification - Recent Threads

How should analog reference outputs be modeled in a pure Verilog REFGEN/BIASGEN cell?

AT202609033946 — Thu, 03 Sep 2026 09:00:05 GMT

Hi,

I am developing a behavioral Verilog model for an IO REFGEN/BIASGEN cell.

In silicon, the cell generates different analog reference voltages:

-Biasp = 2.2V when Enable = high

- Biasp = 3.3V when Enable =low

The model is intended for use in pure digital RTL/gate-level simulations, not Verilog-AMS or mixed-signal simulations.

Since standard Verilog only supports digital values (0, 1, X, Z), what is the recommended industry practice for modeling such analog reference outputs?

Would both 1.5V and 3.3V typically be abstracted as logic '1'?

Any guidance, modeling practices suggested would be appreciated.

Thanks.

HW/SW Co-verification - Embedded assembly code coverage

KS20250205199 — Wed, 02 Sep 2026 11:07:47 GMT

Here is a verification challenge I'm facing and gathering ideas on the possible solutions.

I have a custom processor IP in the design which executes some pre-compiled code. The assembly code is compiled into Verilog ROM. This ROM is then simulated within the design. So the Processor starts executing this ROM code after power up.

Are there any tools or methodologies for collecting embedded firmware code coverage during RTL simulation?

The simplest way would be to create cover bins for every ROM address and measure if all instructions were fetched. But this might not be enough, would be good to see if assembly code branches are covered.

Please share your experience, thoughts or ideas you might have seen in similar cases.

Thanks

SimVision 25.03-s006: Toolbar icons nearly transparent over RDP on AlmaLinux 9.5

MH202503252452 — Thu, 30 Jul 2026 17:07:33 GMT

We are experiencing a rendering issue with SimVision 25.03-s006 on AlmaLinux 9.5 when accessing the system through an RDP session. The application starts and operates normally, but the toolbar icons are rendered almost transparent or heavily washed out, making them difficult to recognize. Only the toolbar icons are affected; all other user interface elements, including menus, dialogs, text, waveforms, and the rest of the application, are displayed correctly. The issue is fully reproducible and occurs every time SimVision is started via RDP. The RDP client is Remmina 1.4.25 using FreeRDP 2.6.1. Since only the icons are affected while the rest of the GUI is rendered correctly, the problem appears to be related to icon alpha blending or Qt icon rendering. We would like to know whether this is a known issue with SimVision 25.03-s006 in an RDP/xrdp environment on RHEL/AlmaLinux 9, and whether a workaround or patch is available.

Is it possible to create a register block that contain multiple register maps with reg_verifier?

NH202509219257 — Wed, 28 Jan 2026 07:26:41 GMT

Hi, I'm considering moving to reg_verifier for register model generation. However, I'm having trouble to create multiple address maps for the same hardware registers.
I want to generate a model with structure like this:

So I tried:
<ipxact:memoryMap>
<ipxact:addressBlock>
// block map 1
...
</ipxact:addressBlock>

<ipxact:addressBlock>
// block map 2
...
</ipxact:addressBlock>
...
</ipxact:memoryMap>
And what i got:

Is there any ways to resolve this? Please let me know.

Best regards,

Son

I'm using RHEL 8.10, and XCELIUM MAIN version 23.09_013 isn't working properly.

CH20260126886 — Tue, 27 Jan 2026 01:04:55 GMT

I'm using RHEL 8.10, and XCELIUM MAIN version 23.09_013 isn't working properly. Is there a problem with the OS? The log is as follows.

//===================================================================

csi-xmsim - CSI: Command line:
xmsim
-f ./test_sim/xcelium.d/run.lnx8664.23.09.d/smidc203_3677635/xmsim.args
-MESSAGES
+EMGRLOG xrun.log
-XLSTIME 1769475002
-XLKEEP
-XLMODE ./xcelium.d/run.lnx8664.23.09.d
-RUNMODE
-CDSLIB ./xcelium.d/run.lnx8664.23.09.d/cds.lib
-HDLVAR ./xcelium.d/run.lnx8664.23.09.d/hdl.var
-XLNAME xrun
-XLVERSION TOOL: xrun(64) 23.09-s013
-XLNAME ./xcelium.d/run.lnx8664.23.09.d/smidc203_3677635
-CHECK_VERSION TOOL: xrun(64) 23.09-s013
-LOG_FD 4
-LOG_FD_NAME xrun.log
-cmdnopsim
-runlock ./test_sim/xcelium.d/run.lnx8664.23.09.d/.xmlib.lock
-runscratch ./test_sim/xcelium.d/run.lnx8664.23.09.d/smidc203_3677635

csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: xmsim(64) 23.09-s013 (CL: 680443 )
HOSTNAME: smidc203
OPERATING SYSTEM: Linux 4.18.0-553.el8_10.x86_64 #1 SMP Fri May 10 15:19:13 EDT 2024 x86_64
MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x50153ec)
Stream rts_xfer
-----------------------------------------------------------------

csi-xmsim - CSI: Cadence Support Investigation, recording details
External Code in function: <unavailable> offset -65519
External Code in function: <unavailable> offset -65536
Simulator Snap Shot: gd (SSS_GD) in snapshot worklib.tb:v (SSS)
Intermediate File: array of pointers (IF_PTRBLK) in snapshot worklib.tb:v (SSS)
Error: Error processing stack frame(8) - skipping rest of frame!
External Code in function: <unavailable> offset -65535
Simulator Snap Shot: root (SSS_ROOT) in snapshot worklib.tb:v (SSS)
Intermediate File: root (IF_ROOT) in snapshot worklib.tb:v (SSS)
Intermediate File: data block (IF_BLK) in snapshot worklib.tb:v (SSS)
Simulator Snap Shot: dynlib (SSS_DYNLIB) in snapshot worklib.tb:v (SSS)
External Code in function: <unavailable> offset -65531
csi-xmsim - CSI: investigation complete took 0.019 secs, send this file to Cadence Support

The bloackbox option "-jg_bbmod" does not work

JS202601054953 — Tue, 06 Jan 2026 03:49:22 GMT

Dear all,

Does anyone knows how to successfully do blackboxing on certain modules when running JasperGold UNR?
The blackbox option in Product Version 2024.09 is -jg_bbmod, and I passed it to the command line bwloe:
xrun
-nohal
-bb_celldefine
-jg
-unr
-xmlibdirname ../../xcelium.d
-R
-jg_coverage all
-covoverwrite
-inst_top top_tb.dut
-l unr_run.log
-jg_analyze_opts -bb_sv_bind
-input jasper_unr.tcl
-jg_pre_tcl pre.tcl
-jg_periodicexport 240m
-covdb ../../temp
-covtest ../../temp_unr
-jg_bbmod sram_wrapper

However, I sitll got an error message on the blackboxed module.
analyze -from_snapshot worklib.sram_wrapper:sv -cdslib ../../cds.lib -hdlvar ../../hdl.var -bb_sv_bind -instTop top_tb.dut
p2p: *F,XMERROR_2813: rlfunc unknown wad struct id 'ifs_sss' PTR(eda1338:304)

Does anyone have the same problem on module/instance blackboxing? Any suggestions would be highly appreciated!

Getting coveritems from Jaspergold

MA202511186935 — Mon, 05 Jan 2026 15:24:53 GMT

Hello,

I was wondering if there is a way to report the coveritems generated from coverage measurement in Jaspergold? Maybe something similar to reporting the coverage data as txt or html file?

XMSIM: *E,SST2ER: SST2 interface error: Stale file handle

NP202512229215 — Tue, 23 Dec 2025 11:21:24 GMT

Hi,

I am facing below issue in regression.

xmsim: *E,SST2ER: SST2 interface error: Stale file handle.

Rahul suggested to refer the cadence site and I picked up the first solution (simulation arguments)

Command Addition (While running simulation)

bsub -J -tb /home/shark8x8_c28_workareas3/work_dv/nxg13282_S8_1411_Dec18_v2/data/ida_smarttrx_shark8x8_ic_tb_lib/ida_smarttrx_shark8x8_ic_tb/nccoex/run_test -sim shark_rfe_cfg -tb vsw_M7_RFE_access_csr_reg_test -uvm_test soc_extspi_rfe_access_reg_test -sv -regr -sim_args +uvm_set_config_string=cdns_uvm_sst2_tr_database,db_name,/dev/null

Simulator picking the arguments (Message in log file)

UVM_INFO @0 [UVM_CMDLINE_PROC]: Applying config setting from the command line: +uvm_set_config_string=cdns_uvm_sst2_tr_database,db_name,/dev/null; T=0

New Error popping (Message from logfile)

UVM_INFO @0 /pkg/synopsys-designware-/vip_collection/vip/svt/uart_svt/Q-2020.06-T-20200615/uart_agent_svt/sverilog/src/ncv/svt_uart_agent.svp(520) [run_phase]: svt_uart_agent RUN-FLOW: Finishing...; T=0

SDI/Verilog Transaction Recording Facility Version 24.09-s011

SDI2 Transaction Recording API Version 24.09-s011

*** Error from SDI2:

SDI could not create the SST2 recording database directory:

'/dev/null.shm'.

The error from the Unix mkdir system call is:

'Permission denied'

*** End of error message from SDI2

Vmanager Screenshot

Solution Mentioned in website

Thanks,

Nanda

Missing symbols in a ucis library

AlexOgheri — Thu, 27 Nov 2025 14:04:23 GMT

Hi dear all, I was trying to use cocotb and the pyvsc python based verification library with xcelium versions 23.03 24.03 and 25.03 but trying touse the libucis.so shared library provided by cadence together with the pyvsc leads to:

...

Traceback (most recent call last):
File "/fme/users/aogher/cocotb_first/firstvsc.py", line 29, in <module>
vsc.write_coverage_db('cov.db', fmt='libucis', libucis='libucis.so')
File "/fme/users/aogher/.local/lib/python3.9/site-packages/vsc/__init__.py", line 113, in write_coverage_db
LibFactory.load_ucis_library(libucis)
File "/fme/users/aogher/.local/lib/python3.9/site-packages/ucis/lib/LibFactory.py", line 42, in load_ucis_library
libucis.load_ucis_library(lib)
File "/fme/users/aogher/.local/lib/python3.9/site-packages/ucis/lib/libucis.py", line 146, in load_ucis_library
func = proto((f, _lib), attr)
AttributeError: /fme/cae/cadence/XCELIUMMAIN25.03.001/LINUX/tools.lnx86/lib/64bit/libucis.so: undefined symbol: ucis_CreateHistoryNode

can this functionality perhaps be implemented in the cadence ucis library in the future or is it somewhere else in the cadence xcelium libraries perhaps ??

kind rgds

Alessandro Ogheri

Ogheri Consulting GmbH

How to initiate the secure/non-secure transfers from cadence AHB5 VIP.

RC202510138351 — Wed, 15 Oct 2025 15:39:02 GMT

How to initiate the secure/non-secure transfers from cadence AHB5 VIP. Also please provide the necessary configuration and transaction item details.
Please provide us the pseudo code for various INCR and WRAP burst transfers with different beats for AHB5 and AXI4 VIP.

Testable and testconstraint attribute supports in reg_verifier?

DR202509011451 — Mon, 01 Sep 2025 13:05:55 GMT

Hi,

I have added testable and testconstraint attributes to IP-XACT XML. While converting XML to RAL model using reg_verifier tool those attributes ignored and genrated RAL model does not contain these attribute. Does reg_verifier supports these attributes? its 1685-2014 IPXACT format

Code coverage syntax for scripting tcl exclusion file

CC202508295120 — Fri, 29 Aug 2025 16:01:57 GMT

Where can I found the syntax for scripting a tcl file for exclusion on coverage when using xcelium

I have a sample , but what is the syntax to write my own ecxlusion conditions

 exclude -covered -inst work.Design(rtl).gen_Main_dls.i_Design_Main_dls  -expression 9.3.4   -comment " something "
or
 exclude -covered -inst work.Design(rtl).gen_Main_dls.i_Design_Main_dls  -block 3  -comment " something "

Thanks

Exclusion of Signals Across Hierarchy for Toggle Coverage using CCF File

WA20250805177 — Tue, 19 Aug 2025 20:35:05 GMT

We are currently working on excluding specific signals from toggle coverage in the top-level module using the exclude.list file in the CCF. The exclusion is applied using the following regular expression:
-ere module top\.req_pkt.*\.ovlddeep
This works as intended for the signal instance in the top module. However, the same signal (ovlddeep) is propagated down to lower-level (descendant) modules through hierarchical connections. We expected the exclusion to apply to these lower-level instances as well, but it appears that the exclusion rule only targets the top-level instance. As a result, we would need to write separate exclusion rules for each module where the signal appears.
Query:

1) Is there a way to exclude a signal (e.g., ovlddeep) across all hierarchical instances from the top-level down, using a single rule or a more generic approach in the CCF file?

2) Are we missing any specific syntax or configuration that enables hierarchical exclusion for toggle coverage?

3) If not supported, can this be considered a limitation, and are there recommended best practices to handle such cases?

Objective:
Looking for a scalable and maintainable method to exclude signals passed through multiple levels of hierarchy without duplicating exclusion rules for each module instance.
Thanks,
-Wadood

Want to run Vmanager in batch mode

PB20250805136 — Tue, 05 Aug 2025 11:20:43 GMT

How to check the status of a regression test after launching it in batch mode

We used the following cmds to trigger a regression test:

The run.tcl script contains:

This successfully launches the test — I can see it running in the vManager GUI. However, I now want to fetch the current status of the test (e.g., whether it’s still running or completed) from the command line. I am also looking for the appropriate commands or arguments to extract a report summarizing the test run results. Kindly help me on this.

Can I change *.ucd type of file into .json to add svseed, coverpoints

SV202408068842 — Wed, 16 Jul 2025 15:12:08 GMT

Hi,

Can I get the details of covergroup details like coverpoint, no of bins, score and test svseed from .ucd into .json format?

vmanager: custom result evaluation

ND202411057246 — Fri, 04 Jul 2025 07:34:36 GMT

Hi all,

I would like to implement a "custom result evaluation" that can influence the test status reported in the dashboard in vmanager. What I have in mind is

open a sim result file
perform some calculations and compare results to specs
contribute to the status pass/fail (along with other stuff, uvm errors, assertions)

Does anyone have a recipe for this?

Cheers

How to eliminate DLCSMD errors in Xcelium's xrun

Celluk — Wed, 28 May 2025 14:02:26 GMT

Hello,

I am using cocotb in python to simulate SystemVerilog files and while there is no issue with other simulators such as modelsim, I came accross DLCSMD error in xrun. I have looked previous similar questions and I know that one can eliminate by changing the source with such as ifdefs however I have a lot of submodules that I cannot change the internal codes (that is not practical also) and I also want to override if there are duplicate codes. For example, in terms of modelsim's behaviour it overrides the same packages, however as can be seen below xrun cannot override them:

xmvlog: *E,DLCSMD: Dependent checksum verilog_package top.cva6_config_pkg:sv (VST) doesn't match with
the checksum that's in the header of: verilog_package top.ariane_axi:sv (VST).
import ariane_axi::*;
 |

I thought another solution can be giving a clean file list however this is also not practical for me for such a big project. Getting them by recursively and override duplicates is better for me. I want to eliminate this error by giving a flag to xrun if possible. I thought this possible flag can be about disabling checksum control or enabling overrides for duplicate files-packages however I couldn't find a flag for my needs.

In short, is it possible to disable this error because it is not an actual error for me?

Functional Coverage at SOC or Sub System Level

TM202505254140 — Sun, 25 May 2025 08:13:09 GMT

Hi All,

At subsystem or SOC verification level,

let’s say there are three IPs integrated : IP1, IP2 and IP3.

Individually from block level verification, all IPs functional coverage is achieved 100%.
IP1 FC 100%
IP2 FC 100%
IP3 FC 100%

But at the subsystem level, when I run some tests or regression, functional coverage is still 60 to 70%. What would be the understanding here?

case_1 : We need to still add tests to make 100% coverage even at SOC level
case_2 : Getting coverage (code or FC) 70% at SOC level is still acceptable, no need to wait for 100% coverage since individually all IPs are already verified.

So, Now I need to sign-off. Can I proceed with just 70% coverage at SOC level,
requesting everyone to share thoughts here.
I am interesting in measuring sign off factors at SOC or sub system level.

Kindly provide your inputs.

Simple Assertion for Counter

TM202505254140 — Sun, 25 May 2025 08:09:54 GMT

Hi all,

Question_1 : Assertion requirement :

When Enable is HIGH, counter should be increment to previous clock cycle value, when Enable is LOW, counter should keep same value as previous cycle.

Below is my understanding. May I know is this satisfying the requirement or require changes?

property p1;

@(posedge clk) Enable |=> (count == $past(count+1));

endproperty

Question_2 : also, do we require one more property for else condition. Like

property p2;

@(posedge clk) (!Enable) |=> (count == $past(count));

endproperty

Is only one property (p1) is sufficient for above requirement.

Kindly suggest

SimVision: how to find all signals in the database matching a specific pattern?

ES20241003727 — Mon, 21 Apr 2025 23:14:54 GMT

Let's imagine I have a signal in my waveform database like test.top.channel_0.subChannel_A.mySignal.

My design has many identical channels and each channel has many identical sub-channels, so the following signals also exist in the waveform database:

test.top.channel_0.subChannel_A.mySignal
test.top.channel_0.subChannel_B.mySignal
test.top.channel_1.subChannel_A.mySignal
test.top.channel_1.subChannel_B.mySignal
...

I would like to add every instance of mySignal that exists in the design to the waveform. Ideally, I would like to do this by just specifying a wildcard/glob pattern, so I can find and add all signals in the design/database of the form:

test.top.channel_*.subChannel_*.mySignal

How can I do this with SimVision?

Initially I thought the "Design Search" window could find all the signals for me, but it seems like there is no option in Design Search to match against the entire hierarchical signal/path name - you can match against just the last part of the scope with the "Consider:" option set to "Scopes":

or just the signal/variable name with the "Consider:" option set to "Signals/Variables":

but not against the entire hierarchal path at once (the "All Design Elements" option for "Consider:" seems to match against each piece of the hierarchy instead of the entire hierarchy path as a whole).

My design might also have signals of the form test.top.someOtherBlock.mySignal that I do NOT want returned, so simply searching for all signals named "mySignal" regardless of hierarchy won't work - I really need to match against the full hierarchy path, with wildcards.

I tried looking at the SimVision TCL command reference to see if there was a way to search through the database/design browser using TCL, but I couldn't find anything useful.

Does anyone have any suggestions on ways to do this?

The simulation finished - Interactive session ending soon

swetha99 — Fri, 11 Apr 2025 17:31:08 GMT

Hello Everyone,

I am trying to run my mixed signal testbench using cadence xcelium. When I try to open the terminal interactively, it says - 'This simulation finished ...'

Please find below screenshot:

Can someone please guide?

Thank you.

Sincerely,

Swetha. C

I observe following error when running xrun -sv

Tarique mohd — Tue, 01 Apr 2025 15:12:43 GMT

Design hierarchy summary:
Instances Unique
Modules: 2 2
Verilog packages: 0 1
Registers: 15 15
Scalar wires: 12 -
Always blocks: 2 2
Initial blocks: 4 4
Pseudo assignments: 4 -
Simulation timescale: 100ps
Writing initial simulation snapshot: worklib.tb_light_fsm:sv
Loading snapshot worklib.tb_light_fsm:sv .................... Done
xcelium> source /eda/cadence/2023-24/RHELx86/XCELIUM_23.03.007/tools/xcelium/files/xmsimrc
xcelium> run
xmsim: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: xmsim(64) 23.03-s007
HOSTNAME: icdtsmc28nm.ewi.tudelft.nl
OPERATING SYSTEM: Linux 4.18.0-553.22.1.el8_10.x86_64 #1 SMP Wed Sep 25 09:20:43 UTC 2024 x86_64
MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x4aa4ccc)
Stream rts_xfer
-----------------------------------------------------------------
csi-xmsim - CSI: Cadence Support Investigation, sending details to /users/mtarique/28nm/T28HPCP/SV_code/xmsim_4106232.err
csi-xmsim - CSI: investigation complete, send /users/mtarique/28nm/T28HPCP/SV_code/xmsim_4106232.err to Cadence Support

Pass variables to tcl script in Xcelium

JF202503209845 — Thu, 20 Mar 2025 17:39:12 GMT

Hello,

I'm trying to pass a Variable through a command line input in the environment, so that my tcl script can take this for its startup initialization.

xrun ... -command_that_sets_sets_a_variable -input "start_script_that_likes_to_read_a_variable.tcl" ...

The idea is that my tcl script loads different configs for SimVision depending on a string I input in the command line. That way I can simply swap out a word in my command line and Xcelium loads (for example) waveforms in a way I want/starts or not/sets breakpoints/whatever. I've tried a few options, but I either didn't understand the documentation or I've searched on the wrong end.

Kind regards
Jan

waveform.wsf syntax manual

HN202503109055 — Mon, 10 Mar 2025 21:13:17 GMT

Hi,

Is there any manual for editting the waveform.wsf file, that is created when saving user state in Verisium Debug?

Up till now, I made some customizations, and when I saved, I saw how it is written, and I editted it, but now I'm trying to add value highlighting, but it does not save anything in the wsf file.

Is there any LRM that defines which commands can be used?

Thanks

EEnet Library Path

DanielTX — Tue, 04 Mar 2025 10:11:55 GMT

Hello,

I'm trying to add EEnet Library with component list (capacitors, MOS, current sources...) into virtuoso for modelling purposes, but I cannot find it.

I've looked into $XCELIUM_HOME/tools/affirma_ams/etc/dms/ but i found only systemVerilog package EE_pkg.

Could someone help me with the path for EEnet Library ?

Thank you!