Functional Verification - Recent Threads

Is it possible to create a register block that contain multiple register maps with reg_verifier?

NH202509219257 — Wed, 28 Jan 2026 07:26:41 GMT

Hi, I'm considering moving to reg_verifier for register model generation. However, I'm having trouble to create multiple address maps for the same hardware registers.
I want to generate a model with structure like this:

So I tried:
<ipxact:memoryMap>
<ipxact:addressBlock>
// block map 1
...
</ipxact:addressBlock>

<ipxact:addressBlock>
// block map 2
...
</ipxact:addressBlock>
...
</ipxact:memoryMap>
And what i got:

Is there any ways to resolve this? Please let me know.

Best regards,

Son

I'm using RHEL 8.10, and XCELIUM MAIN version 23.09_013 isn't working properly.

CH20260126886 — Tue, 27 Jan 2026 01:04:55 GMT

I'm using RHEL 8.10, and XCELIUM MAIN version 23.09_013 isn't working properly. Is there a problem with the OS? The log is as follows.

//===================================================================

csi-xmsim - CSI: Command line:
xmsim
-f ./test_sim/xcelium.d/run.lnx8664.23.09.d/smidc203_3677635/xmsim.args
-MESSAGES
+EMGRLOG xrun.log
-XLSTIME 1769475002
-XLKEEP
-XLMODE ./xcelium.d/run.lnx8664.23.09.d
-RUNMODE
-CDSLIB ./xcelium.d/run.lnx8664.23.09.d/cds.lib
-HDLVAR ./xcelium.d/run.lnx8664.23.09.d/hdl.var
-XLNAME xrun
-XLVERSION TOOL: xrun(64) 23.09-s013
-XLNAME ./xcelium.d/run.lnx8664.23.09.d/smidc203_3677635
-CHECK_VERSION TOOL: xrun(64) 23.09-s013
-LOG_FD 4
-LOG_FD_NAME xrun.log
-cmdnopsim
-runlock ./test_sim/xcelium.d/run.lnx8664.23.09.d/.xmlib.lock
-runscratch ./test_sim/xcelium.d/run.lnx8664.23.09.d/smidc203_3677635

csi-xmsim - CSI: *F,INTERR: INTERNAL EXCEPTION
Observed simulation time : 0 FS + 0
-----------------------------------------------------------------
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: xmsim(64) 23.09-s013 (CL: 680443 )
HOSTNAME: smidc203
OPERATING SYSTEM: Linux 4.18.0-553.el8_10.x86_64 #1 SMP Fri May 10 15:19:13 EDT 2024 x86_64
MESSAGE: T(0): sv_seghandler - trapno -1 addr(0x50153ec)
Stream rts_xfer
-----------------------------------------------------------------

csi-xmsim - CSI: Cadence Support Investigation, recording details
External Code in function: <unavailable> offset -65519
External Code in function: <unavailable> offset -65536
Simulator Snap Shot: gd (SSS_GD) in snapshot worklib.tb:v (SSS)
Intermediate File: array of pointers (IF_PTRBLK) in snapshot worklib.tb:v (SSS)
Error: Error processing stack frame(8) - skipping rest of frame!
External Code in function: <unavailable> offset -65535
Simulator Snap Shot: root (SSS_ROOT) in snapshot worklib.tb:v (SSS)
Intermediate File: root (IF_ROOT) in snapshot worklib.tb:v (SSS)
Intermediate File: data block (IF_BLK) in snapshot worklib.tb:v (SSS)
Simulator Snap Shot: dynlib (SSS_DYNLIB) in snapshot worklib.tb:v (SSS)
External Code in function: <unavailable> offset -65531
csi-xmsim - CSI: investigation complete took 0.019 secs, send this file to Cadence Support

The bloackbox option "-jg_bbmod" does not work

JS202601054953 — Tue, 06 Jan 2026 03:49:22 GMT

Dear all,

Does anyone knows how to successfully do blackboxing on certain modules when running JasperGold UNR?
The blackbox option in Product Version 2024.09 is -jg_bbmod, and I passed it to the command line bwloe:
xrun
-nohal
-bb_celldefine
-jg
-unr
-xmlibdirname ../../xcelium.d
-R
-jg_coverage all
-covoverwrite
-inst_top top_tb.dut
-l unr_run.log
-jg_analyze_opts -bb_sv_bind
-input jasper_unr.tcl
-jg_pre_tcl pre.tcl
-jg_periodicexport 240m
-covdb ../../temp
-covtest ../../temp_unr
-jg_bbmod sram_wrapper

However, I sitll got an error message on the blackboxed module.
analyze -from_snapshot worklib.sram_wrapper:sv -cdslib ../../cds.lib -hdlvar ../../hdl.var -bb_sv_bind -instTop top_tb.dut
p2p: *F,XMERROR_2813: rlfunc unknown wad struct id 'ifs_sss' PTR(eda1338:304)

Does anyone have the same problem on module/instance blackboxing? Any suggestions would be highly appreciated!

Getting coveritems from Jaspergold

MA202511186935 — Mon, 05 Jan 2026 15:24:53 GMT

Hello,

I was wondering if there is a way to report the coveritems generated from coverage measurement in Jaspergold? Maybe something similar to reporting the coverage data as txt or html file?

XMSIM: *E,SST2ER: SST2 interface error: Stale file handle

NP202512229215 — Tue, 23 Dec 2025 11:21:24 GMT

Hi,

I am facing below issue in regression.

xmsim: *E,SST2ER: SST2 interface error: Stale file handle.

Rahul suggested to refer the cadence site and I picked up the first solution (simulation arguments)

Command Addition (While running simulation)

bsub -J -tb /home/shark8x8_c28_workareas3/work_dv/nxg13282_S8_1411_Dec18_v2/data/ida_smarttrx_shark8x8_ic_tb_lib/ida_smarttrx_shark8x8_ic_tb/nccoex/run_test -sim shark_rfe_cfg -tb vsw_M7_RFE_access_csr_reg_test -uvm_test soc_extspi_rfe_access_reg_test -sv -regr -sim_args +uvm_set_config_string=cdns_uvm_sst2_tr_database,db_name,/dev/null

Simulator picking the arguments (Message in log file)

UVM_INFO @0 [UVM_CMDLINE_PROC]: Applying config setting from the command line: +uvm_set_config_string=cdns_uvm_sst2_tr_database,db_name,/dev/null; T=0

New Error popping (Message from logfile)

UVM_INFO @0 /pkg/synopsys-designware-/vip_collection/vip/svt/uart_svt/Q-2020.06-T-20200615/uart_agent_svt/sverilog/src/ncv/svt_uart_agent.svp(520) [run_phase]: svt_uart_agent RUN-FLOW: Finishing...; T=0

SDI/Verilog Transaction Recording Facility Version 24.09-s011

SDI2 Transaction Recording API Version 24.09-s011

*** Error from SDI2:

SDI could not create the SST2 recording database directory:

'/dev/null.shm'.

The error from the Unix mkdir system call is:

'Permission denied'

*** End of error message from SDI2

Vmanager Screenshot

Solution Mentioned in website

Thanks,

Nanda

RE: XMSIM: *E,SST2ER: SST2 interface error: Stale file handle

StephenH — Wed, 24 Dec 2025 10:06:34 GMT

I tried using the "codec" example from the UVM-1.2 installation, and the plusarg approach produces the errors but the test continues to run OK and passes, without creating the SHM file. As per the application note that you refer to, the simulator logs report:

Message!     [SDI/Verilog]                                                     
    SDI recording is disabled because of the failure to open a
recording database,with filename = '/dev/null'
Current simulation time = 286250                                                                         
    "/grid/avs/install/xcelium/2409/24.09.011/tools/methodology/UVM/CDNS-1.2/additions/sv/cdns_recording.svh", 350: $sdi_open(db_name_l,use_existing_db,use_compression);

I note that you mention vManager - you might need to modify your log filters to suppress the SDI error in order for the test to be shown as passing in vManager, although in my trial with uvm.fpt and cdsn_sim.flt it was not causing vm_scan.pl to identify any failures.

RE: XMSIM: *E,SST2ER: SST2 interface error: Stale file handle

StephenH — Wed, 24 Dec 2025 09:30:39 GMT

Hi Nanda.

Does the simulation complete despite this error?

RE: Missing symbols in a ucis library

StephenH — Thu, 27 Nov 2025 14:23:48 GMT

Hi Alex.

So far as I'm aware there is no support for UCIS history in any of the Cadence tooling, as equivalent functionality is implemented in other Cadence technology.
We can't discuss road-maps or take change requests via this public forum, so I'd encourage you to login to https://support.cadence.com/ and file a support request there, asking for this feature, so that a member of the support team can discuss your requirements and if appropriate, follow up with R&D.

Thanks.
Steve

Missing symbols in a ucis library

AlexOgheri — Thu, 27 Nov 2025 14:04:23 GMT

Hi dear all, I was trying to use cocotb and the pyvsc python based verification library with xcelium versions 23.03 24.03 and 25.03 but trying touse the libucis.so shared library provided by cadence together with the pyvsc leads to:

...

Traceback (most recent call last):
File "/fme/users/aogher/cocotb_first/firstvsc.py", line 29, in <module>
vsc.write_coverage_db('cov.db', fmt='libucis', libucis='libucis.so')
File "/fme/users/aogher/.local/lib/python3.9/site-packages/vsc/__init__.py", line 113, in write_coverage_db
LibFactory.load_ucis_library(libucis)
File "/fme/users/aogher/.local/lib/python3.9/site-packages/ucis/lib/LibFactory.py", line 42, in load_ucis_library
libucis.load_ucis_library(lib)
File "/fme/users/aogher/.local/lib/python3.9/site-packages/ucis/lib/libucis.py", line 146, in load_ucis_library
func = proto((f, _lib), attr)
AttributeError: /fme/cae/cadence/XCELIUMMAIN25.03.001/LINUX/tools.lnx86/lib/64bit/libucis.so: undefined symbol: ucis_CreateHistoryNode

can this functionality perhaps be implemented in the cadence ucis library in the future or is it somewhere else in the cadence xcelium libraries perhaps ??

kind rgds

Alessandro Ogheri

Ogheri Consulting GmbH

How to initiate the secure/non-secure transfers from cadence AHB5 VIP.

RC202510138351 — Wed, 15 Oct 2025 15:39:02 GMT

How to initiate the secure/non-secure transfers from cadence AHB5 VIP. Also please provide the necessary configuration and transaction item details.
Please provide us the pseudo code for various INCR and WRAP burst transfers with different beats for AHB5 and AXI4 VIP.

Pass variables to tcl script in Xcelium

JF202503209845 — Thu, 20 Mar 2025 17:39:12 GMT

Hello,

I'm trying to pass a Variable through a command line input in the environment, so that my tcl script can take this for its startup initialization.

xrun ... -command_that_sets_sets_a_variable -input "start_script_that_likes_to_read_a_variable.tcl" ...

The idea is that my tcl script loads different configs for SimVision depending on a string I input in the command line. That way I can simply swap out a word in my command line and Xcelium loads (for example) waveforms in a way I want/starts or not/sets breakpoints/whatever. I've tried a few options, but I either didn't understand the documentation or I've searched on the wrong end.

Kind regards
Jan

RE: Pass variables to tcl script in Xcelium

JF202503209845 — Thu, 18 Sep 2025 13:38:42 GMT

Hi Stephen,

Solved my Problem, thank you.

Kind regards,

Jan

RE: Testable and testconstraint attribute supports in reg_verifier?

StephenH — Wed, 10 Sep 2025 07:25:10 GMT

If you need these features to be added to reg_verifier and can explain what functionality reg_verifier is supposed to infer from them, then please submit a formal request via https://support.cadence.com/ - we cannot do this through the public forums.

I'm not really clear what these attributes are expected to map to in UVM_REG functionality, and it seems that even the IPXACT developers avoided answering the question (https://forums.accellera.org/topic/5830-ip-xact-testable-and-testconstraint/ for example).

Testable and testconstraint attribute supports in reg_verifier?

DR202509011451 — Mon, 01 Sep 2025 13:05:55 GMT

Hi,

I have added testable and testconstraint attributes to IP-XACT XML. While converting XML to RAL model using reg_verifier tool those attributes ignored and genrated RAL model does not contain these attribute. Does reg_verifier supports these attributes? its 1685-2014 IPXACT format

RE: Testable and testconstraint attribute supports in reg_verifier?

DR202509011451 — Tue, 09 Sep 2025 16:46:48 GMT

Hi,

Thanks for providing reg verifier user guide. I have gone through user guide, don't find information that support of testable and testconstraint attributes in reg _verifier..

Below is the IPXACT XML snippet, applied testable and testconstraint for register field.

RE: Testable and testconstraint attribute supports in reg_verifier?

StephenH — Mon, 01 Sep 2025 14:22:42 GMT

You can find the supported attributes in the reg_verifier user guide here:

RE: Code coverage syntax for scripting tcl exclusion file

StephenH — Mon, 01 Sep 2025 08:30:35 GMT

Please refer to the IMC documentation in the user guide: here

Code coverage syntax for scripting tcl exclusion file

CC202508295120 — Fri, 29 Aug 2025 16:01:57 GMT

Where can I found the syntax for scripting a tcl file for exclusion on coverage when using xcelium

I have a sample , but what is the syntax to write my own ecxlusion conditions

 exclude -covered -inst work.Design(rtl).gen_Main_dls.i_Design_Main_dls  -expression 9.3.4   -comment " something "
or
 exclude -covered -inst work.Design(rtl).gen_Main_dls.i_Design_Main_dls  -block 3  -comment " something "

Thanks

RE: Pass variables to tcl script in Xcelium

StephenH — Wed, 20 Aug 2025 08:33:59 GMT

Hi Jan.

You can pass Tcl commands directly by starting the argument to -input with an "@" symbol:

xrun -input "@set my_var 123" -input my_script_that_reads_my_var.tcl

Hope this helps.

RE: SimVision: how to find all signals in the database matching a specific pattern?

StephenH — Wed, 20 Aug 2025 08:31:43 GMT

You could probably achieve this using SimVIsion's Tcl scripting, to navigate the design and procedurally add the signals to the waveform. If you wrote such a script, it could be attached to a SimVision GUI button.

However, SimVision is a legacy tool that is not actively developed and I would strongly recommend moving to Verisium Debug, which has far more powerful capabilities including a global search which would easily accomplish what you're asking for. Speak to your local Cadence AE if you want more information on how to use Verisium Debug, or take a look at the collateral under https://support.cadence.com/verisiumdebug

SimVision: how to find all signals in the database matching a specific pattern?

ES20241003727 — Mon, 21 Apr 2025 23:14:54 GMT

Let's imagine I have a signal in my waveform database like test.top.channel_0.subChannel_A.mySignal.

My design has many identical channels and each channel has many identical sub-channels, so the following signals also exist in the waveform database:

test.top.channel_0.subChannel_A.mySignal
test.top.channel_0.subChannel_B.mySignal
test.top.channel_1.subChannel_A.mySignal
test.top.channel_1.subChannel_B.mySignal
...

I would like to add every instance of mySignal that exists in the design to the waveform. Ideally, I would like to do this by just specifying a wildcard/glob pattern, so I can find and add all signals in the design/database of the form:

test.top.channel_*.subChannel_*.mySignal

How can I do this with SimVision?

Initially I thought the "Design Search" window could find all the signals for me, but it seems like there is no option in Design Search to match against the entire hierarchical signal/path name - you can match against just the last part of the scope with the "Consider:" option set to "Scopes":

or just the signal/variable name with the "Consider:" option set to "Signals/Variables":

but not against the entire hierarchal path at once (the "All Design Elements" option for "Consider:" seems to match against each piece of the hierarchy instead of the entire hierarchy path as a whole).

My design might also have signals of the form test.top.someOtherBlock.mySignal that I do NOT want returned, so simply searching for all signals named "mySignal" regardless of hierarchy won't work - I really need to match against the full hierarchy path, with wildcards.

I tried looking at the SimVision TCL command reference to see if there was a way to search through the database/design browser using TCL, but I couldn't find anything useful.

Does anyone have any suggestions on ways to do this?

Functional Coverage at SOC or Sub System Level

TM202505254140 — Sun, 25 May 2025 08:13:09 GMT

Hi All,

At subsystem or SOC verification level,

let’s say there are three IPs integrated : IP1, IP2 and IP3.

Individually from block level verification, all IPs functional coverage is achieved 100%.
IP1 FC 100%
IP2 FC 100%
IP3 FC 100%

But at the subsystem level, when I run some tests or regression, functional coverage is still 60 to 70%. What would be the understanding here?

case_1 : We need to still add tests to make 100% coverage even at SOC level
case_2 : Getting coverage (code or FC) 70% at SOC level is still acceptable, no need to wait for 100% coverage since individually all IPs are already verified.

So, Now I need to sign-off. Can I proceed with just 70% coverage at SOC level,
requesting everyone to share thoughts here.
I am interesting in measuring sign off factors at SOC or sub system level.

Kindly provide your inputs.

RE: Functional Coverage at SOC or Sub System Level

StephenH — Wed, 20 Aug 2025 08:27:34 GMT

This is quite an academic question. Coverage is simply a metric to tell you what you have not exercised in your verification process. I think most engineers would not aim to re-verify all the internals of an IP further up the integration levels, thus trying to achieve 100% coverage on the IP makes no sense and would add significantly to the cost of verifying the subsystem or SoC. Focus on verifying the integration of the IP into the subsystem - this tends to be more about exercising use cases and ensuring that the subsystem behaves correctly with the IP in it.

RE: vmanager: custom result evaluation

StephenH — Wed, 20 Aug 2025 08:21:44 GMT

It sounds like you want a manual review step rather than a fully automated one, is that right?

You can define buttons attached to custom Tcl scripts in the vManager GUI, these can be sensitive to the selected items in the GUI, so in principle it would be possible to define a button/script that is sensitive to the selected run, opening some kind of Tk GUI that you then use to enter additional information, and then have the script push that into vManager to contribute to the test status or to update run user-defined attributes.

Alternatively you could go full-custom and use the vManager REST API (vAPI) to interact with every aspect of the runs and failure signatures.

vmanager: custom result evaluation

ND202411057246 — Fri, 04 Jul 2025 07:34:36 GMT

Hi all,

I would like to implement a "custom result evaluation" that can influence the test status reported in the dashboard in vmanager. What I have in mind is

open a sim result file
perform some calculations and compare results to specs
contribute to the status pass/fail (along with other stuff, uvm errors, assertions)

Does anyone have a recipe for this?

Cheers