Hardware/Software Co-Development, Verification and Integration - Recent Threads

IP6514E Driver for Nand Flash

XJ202511099616 — Mon, 10 Nov 2025 02:44:45 GMT

Hi, I am adapting Nand flash based on QSPI Flash controller, part number:IP6514E, but the kernel only supports 'HP-NFC' and I couldn't find one suitable for IP6514E. I am not sure if the official version of the driver code is provided.Looking forward to your reply.

ADE matlab integration to launch MATLAB

HL202503171417 — Tue, 18 Mar 2025 08:20:39 GMT

Hello, I intend to interface with MATLAB to enable MATLAB-controlled layout design, EMX simulation, and Spectre simulation operations in ADE.

However, after completing a simulation in ADE Explorer, clicking the "M button" in ADE Explore does not launch MATLAB.

Are there additional environment variables that need to be configured or other requirements?

Thanks in advance!

Best Practices for Hardware-Software Co-Development in Healthcare Devices

JB202501285441 — Tue, 28 Jan 2025 09:57:20 GMT

Hi everyone,

I’m working on a project involving the co-development of hardware and software for a healthcare device. The goal is to build a smart monitoring device capable of tracking patient vitals and transmitting the data to a secure cloud platform for real-time analysis and reporting.

We’re using a Cadence-based design for the hardware, and the software stack includes embedded C for the firmware and Python for data handling on the backend. Here’s a simplified example of how the firmware is set up to transmit data:

#include <stdio.h>
#include <stdint.h>

void sendDataToCloud(uint16_t heartRate, uint16_t oxygenLevel) {
// Simulating data transmission
printf("Sending Data: Heart Rate: %d, Oxygen Level: %d\n", heartRate, oxygenLevel);
}

int main() {
uint16_t heartRate = 72;
uint16_t oxygenLevel = 98;

// Simulating real-time data
while (1) {
sendDataToCloud(heartRate, oxygenLevel);
// Update data dynamically in a real device
}

return 0;
}

Challenges I’m Facing:

Hardware-Software Synchronization: How do you ensure seamless synchronization between hardware-generated signals and software processing in real-time?
Data Security: What are the best practices for encrypting and securing sensitive patient data during transmission and storage?
Testing & Verification: Are there tools or methodologies you recommend for co-verifying hardware and software to identify and resolve integration issues early?

I’ve explored healthcare software development services that specialize in end-to-end solutions for such devices, but I’d love to hear from this community:

Have you worked on similar hardware-software integration for healthcare or IoT devices?
How do you handle real-time data processing and synchronization challenges?
Any recommendations for tools, frameworks, or workflows to improve development efficiency?

Looking forward to your valuable insights. Thanks in advance!

Can't request Tensilica SDK - Error 500

PD202410025735 — Tue, 22 Oct 2024 14:25:12 GMT

Hi,

I'm looking to download Tensilica SDK for evaluation, but I can't get past the registration form:

RE: Can't request Tensilica SDK - Error 500

PD202410025735 — Wed, 23 Oct 2024 08:01:09 GMT

I tried the website with Microsoft Edge and noticed that it now validated my inputs. Firefox did not.

Turns out the form cannot handle non-English characters in names, nor does it accept dashes in username.

I was able to fill in the form now, but with restrictions on my PC username and real name

How to design enhancement mode eGaN (EPC8002) switch in cadence

IU202408064943 — Tue, 06 Aug 2024 08:44:04 GMT

Hi,

I need to design EPC8002 eGaN switch in cadence. Can someone provide me step by step guide on hoe to add EPC8002 into my cadence. I am working on BCD180.

Thank you

Ihsan

Sweep Function Error

iaty — Fri, 21 Jun 2024 10:32:44 GMT

When I try to implement the sweep inside my verilog file, I get the following errors.

/// Function

swp2 sweep param=Ndiscmin values=[0.011 0.5055 1] { //// Line 63
tran2 tran start=0 stop=1300n errpreset=conservative
}

The code used to Replace Cache useing TCL command

Laoy — Fri, 19 Apr 2024 10:16:17 GMT

use the DBO function DboLib_RepalceCache to do the job of "Replace cache"

in order to easy the job , type the code below . the code is a wrapper of the function metioned above

set lStatus [DboState]
set lSession $::DboSession_s_pDboSession
DboSession -this $lSession
set lDesignsIter [$lSession NewDesignsIter $lStatus]
set lDesign [$lDesignsIter NextDesign $lStatus]
set lNullObj NULL

set oldLibName [DboTclHelper_sMakeCString "E:\\PROJECT_WORKLIB.OLB"]
set newLibName [DboTclHelper_sMakeCString "E:\\MCU_PARTS_LIB.OLB"]

#DboLib_ReplaceCache wrapper
proc ReplaceCacheByName {partName} {
global oldLibName
global newLibName
global lDesign
set lPartStr [DboTclHelper_sMakeCString $partName]
#set lNewStr [DboTclHelper_sMakeCString $newName]
$lDesign ReplaceCache $lPartStr $oldLibName $lPartStr $newLibName 0 1
}

then use the tcl command like below to do the real job :

ReplaceCacheByName "CL10B104KB8NNNC_C12"

How to turn vavlog IO width mismatch error to warning?

jingxiang — Wed, 13 Sep 2023 07:15:52 GMT

Hi, all.

When I use vavlog to compile verilog rtl, it will recognize IO width mismatch problem as a fatal error.

How to turn the error into warning?

VCS can use -error=noIOPCWM to ingore the error.

Is vavlog has similar arguments?

Xtensa compiler issue

MxL Hunter — Thu, 01 Dec 2022 09:31:48 GMT

I have a Xtensa compiler issue that the compilation for switch case would be optimized in some patterns and leads to unexpected result. I cross-checked the assembly code and found that such compiler optimization seems to be similar to the tree-switch-conversion feature in GCC compiler

https://gcc.gnu.org/onlinedocs/gcc-9.1.0/gcc/Optimize-Options.html
-ftree-switch-conversion
Perform conversion of simple initializations in a switch to initializations from a scalar array. This flag is enabled by default at -O2 and highe

Unfortunately I don't find any similar compiler option(like -fno-tree-switch-conversion) in Xtensa compiler(XCC) to enable/disable such feature and such feature seems like enabled in XCC by default even if I'm using -O0 for the least optimization.

I'm wondering if there's any possible solution to permanently disable such feature in XCC?

PS: The release version of XCC compiler I'm using is RD-2012.5

Thanks!

RE: Xtensa compiler issue

StephenH — Thu, 01 Dec 2022 15:31:04 GMT

I see that you've also filed the same question as a support ticket via support.cadence.com so I'll let the dedicated Tensilica support team respond to you via that channel.

Note that your compiler version is 10 years old, you should consider using a newer and supported version!

RE: Xtensa compiler issue

Andrew Beckett — Thu, 01 Dec 2022 10:33:33 GMT

As a moderator of some of the other forums and the person who approved your post, to answer your question about why this was marked as potentially spam, it's because your post had a non-Cadence URL link in it. Obviously your post isn't spam, but this is just a way of cutting down the large amounts of noise we were getting with link spammers.

Regards,

Andrew

RE: NClaunch : ncelab: *E,CUVHNF error

Rspatel — Wed, 08 Dec 2021 13:48:53 GMT

Thank you very much TAM1. One more doubt is xmelab i am using that will give answer for the same *E,CUVHNF ?

NClaunch : ncelab: *E,CUVHNF error

Anklon — Sat, 03 Jun 2017 07:24:34 GMT

I'm trying to simulate a practice code . Verilog verification of my code do not give any error.But when I try to elaborate, this error is being showed:

ncelab: *E,CUVHNF (./FSM_test.v,17|20): Hierarchical name component lookup failed at 'l'

What does this mean? How can I debug this error ? Is there any archive or list of possible error list so that I don't have to ask in forum to understand the errors.

xtensa download

ibrahim06 — Thu, 23 Sep 2021 16:12:45 GMT

I want to download Xtensa C/C++ Compiler (XCC) . I dont know where to download. Please help me.

Path mapping for C Firmware source files when debugging

29erpete — Mon, 25 Feb 2019 16:24:37 GMT

Hi,

i am compiling firmware under Windows transfer the binaries and the sources to Linux to simulate/debug there. The problem is that the paths in the DWARF debug info of the .elf file are the absolute Windows paths as set by the compiler so they are useless under Linux. Is it possible to configure mappings of these paths to the Linux paths when simulating/debugging like with e.g. GDB (https://sourceware.org/gdb/current/onlinedocs/gdb/Source-Path.html#index-set-substitute_002dpath)?

thx,

Peter

RE: Path mapping for C Firmware source files when debugging

rvphilip — Thu, 03 Jun 2021 19:34:32 GMT

The PX4 source code is stored on Github in the px4/firmware repository. I would recommend that you fork this repository and then clone the source to your local computer. The path is stored in the .debug_str section of the binary, as a NUL-terminated string. You can find the section offset from e.g. readelf -S, and edit the string with emacs. Or write a program to do that. If you are still unable to get it right, I would recommend you try an Enterprise Application Development Services who will get it done for you quickly with very little expense.

RE: Issue With Loudness Normalization

StephenH — Fri, 22 Jan 2021 14:01:38 GMT

Hi Damien. I'm glad you resolved your issue, but please note these forums are for people to discuss issues related to the verification of semiconductor designs, you won't find many people on here who will respond to off-topic discussions about sound cards or Windows.

Best wishes.

Steve

Issue With Loudness Normalization

Damien Lehner — Thu, 21 Jan 2021 12:19:15 GMT

Hello everyone. In recent days, I'm having a weird problem with sound output on my Windows 10 PC. In fact, I can't control the loudness of it. So is there any possibility of PCB of sound card being damaged?

RE: Issue With Loudness Normalization

Damien Lehner — Fri, 22 Jan 2021 12:36:09 GMT

Hey guys, I googled some articles and saw that it's not due to any hardware issue but a Windows setting can solve my problem. And this article helped me to solve it easily.

RE: Rotate padstack in symbol view

ipath — Fri, 22 Jan 2021 05:40:48 GMT

This drove me crazy for some time. With nothing selected, click Edit->Spin first, then select the pad to rotate. (Edit->Spin, not Edit->Move)

Rotate padstack in symbol view

JacobL — Tue, 03 Mar 2009 09:04:04 GMT

Hello!

I'm trying to rotate a padstack in one of my symbols (opened .dra file in allegro 16.2). I want it 90 deg rotated. If I right-click, I find "move", I can pick options if I right click and pick "rotation angle" but it doesn't rotate. I I instead use "rotate" when right clicking, It rotates but I can't get a clean 90 deg rotation, it always seams a bit "tilted". If I pick "Edit->Spin gives me: "No valid items selected for the current operation, exiting.

Would be really nice if someone can answer...

Br, Jacob

Formal Verification Approach for I2C Slave

calciuiulian — Mon, 16 Nov 2020 15:31:30 GMT

Hello,

I am new in formal verification and I have a concept question about how to verify an I2C Slave block.

I think the response should be valid for any serial interface which needs to receive information for several clocks before making an action.

The the protocol description is the following:

I have a serial clock (SCL), Serial Data Input (SDI) and Serial Data Output (SDO), all are ports of the I2C Slave block.

The protocol looks like this:

The first byte which is received by the slave consists in 7bits of sensor address and the 8th bit is the command 0/1 Write/Read.

After the first 8 bits, the slave sends an ACK (SDO = 1 for 1 clock) if the sensor address is correct.

Lets consider only this case, where I want to verify that the slave responds with an ACK if the sensor address is correct.

The only solution I found so far was to use the internal buffer from the block which saves the received bits during 8 clocks. The signal is called shift_s.

I also needed to use internal chip state (state_s) and an internal counter (shift_count_s).

Instead of doing an direct check of the SDO(sdo_o) depending on SDI (sdi_d_i), I used the internal shift_s register.

My question is if my approach is the correct one or there is a possibility to write the verification at a blackbox level.

Below you have the 2 properties: first checks connection from SDI to internal buffer, the second checks the connection between internal buffer and output.

property prop_i2c_sdi_store;
@(posedge sclk_n_i)
$past(i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR)
|-> i2c_bl.shift_s == byte'({ $past(i2c_bl.shift_s), $past(sdi_d_i)});
endproperty
APF_I2C_CHECK_SDI_STORE: assert property(prop_i2c_sdi_store);

property prop_i2c_sensor_addr(sens_addr_sel, sens_addr);
@(posedge sclk_n_i) (i2c_bl.state_s == `STATE_RECEIVE_I2C_ADDR) && (i2c_addr_i == sens_addr_sel) && (i2c_bl.shift_count_s == 7)
##1 (i2c_bl.shift_s inside {sens_addr, sens_addr+1}) |-> sdo_o;
endproperty
APF_I2C_CHECK_SENSOR_ADDR0: assert property(prop_i2c_sensor_addr(0, `I2C_SENSOR_ADDRESS_A0));
APF_I2C_CHECK_SENSOR_ADDR1: assert property(prop_i2c_sensor_addr(1, `I2C_SENSOR_ADDRESS_A1));
APF_I2C_CHECK_SENSOR_ADDR2: assert property(prop_i2c_sensor_addr(2, `I2C_SENSOR_ADDRESS_A2));
APF_I2C_CHECK_SENSOR_ADDR3: assert property(prop_i2c_sensor_addr(3, `I2C_SENSOR_ADDRESS_A3));

PS: i2c_addr_i is address selection for the slave (there are 4 configurable sensor addresses, but this is not important for the case).

Thank you!

RE: Formal Verification Approach for I2C Slave

calciuiulian — Tue, 17 Nov 2020 15:16:28 GMT

Sorry, wrong location. Could be removed by an admin. I created another topic in Verification. Thank you!

SCCM deployment

RNIWeibel — Fri, 06 Nov 2020 06:50:21 GMT

We are having some issues with deploying i. We are looking for the silent command switch for deployment including the licence agreement acceptance.

Ideally we would like a regular MSI that we could install for all users and not in the user content.