The same design can be synthesized by Synopsys (syn-2010.03-SP3). No error happens. When I use Cadence RTL compiler, one error happens. The error information is listed as below.
Library: CORE65GPLVT_nom_1.10V_25C.lib CLOCK65GPLVT_nom_1.10V_25C.lib
Error : Unable to map design without a suitable latch. [MAP-3] [synthesize] : Instance 'U1/full_nx_reg' requires a simple latch. : Check the libraries for necessary latch cell. The cell could be marked unusable. Synthesis failed.
WHEN "10" => IF (full_nx /= '1') THEN wptr_nx <= wptr_reg; empty_nx <= '0'; wen_nx <= '1'; ren_nx <= '0'; IF (wen_nx = '1') THEN wptr_nx <= wptr_suc; END IF; ELSE wen_nx <= '0'; ren_nx <= '0'; END IF;
IF (wptr_suc = rptr_reg) THEN full_nx <= '1'; wen_nx <= '0'; ELSE full_nx <= '0'; END IF;
Could you please give me some suggestions? I 'd appreciate any help I can get.
Thank you very much.
Your library doesnt seem to contain a latch. Please open it and ensure that you have latch cells, and they aren't marked unusable
If you do not want to use latches, please take a look in the HDL Modeling in Encounter® RTL Compiler manual, where it is explained that , depending on the way you code verilog, synthesis can infer a latch rather than a flop in many situations.
P.S: This topic should be moved to "Logic Design" board, because it is an RTL compiler issue, and not a C to Silicon one.
Thanks for reply
Great info! I recently came across your blog and have been reading along. I thought I would leave my first comment. I don’t know what to say except that I have. Cheese
Thanks for sharing this information. I really like your blog post very much. You have really shared a informative and interesting blog post . Magnesium