High-Level Synthesis - Recent Threads

To add asynch. reset at Stratus example-1

SC202501247228 — Tue, 11 Feb 2025 01:11:16 GMT

Hi I'm newbie in HLS

For stratus example-1, I have one question.

I expected that I could add async. reset for all f/f/ but I couldn't add at the output data registers while all other f/fs were synthesized with async. reset.

What I changed was

SC_CTOR( dut )

{

SC_CTREAD( thread_function, clk.pos() );

reset_singal_is( rst, 0 ); --> async_reset_signal_is( rst, 0 );

din.clk_rst( clk, rst ); --> din.clk_rst_async( clk, rst );

dout.clk_rst( clk, rst ); --> dout.clk_rst_async( clk, rst, false);

}

All synthesized f/fs except output data f/f have async. reset.

f/f with async. reset : always_ff( posedge clk or negedge rst)

output data f/f : always_ff(posedge clk)

So what I missed ?

find cells in row next to all same

zehtr — Mon, 25 Sep 2023 02:30:21 GMT

I have special capacitor cells in layout. sometimes they abut next to each other in cell row. Need to find all the places where there are many of these next to. When find them,get the X1 X2 of where they are in a row. How to complete task?

write placement blockage around cell

zehtr — Mon, 25 Sep 2023 02:26:07 GMT

I have special placed cell. I need to find cell and draw placement blockage for full width of cell for the complete height of the design. From top to bottom of the design. How to complete task?

Delivered example STRATUS_20.24.100/share/stratus/collateral/examples/simple_dmac_apb is not able to work.

mxlusereight — Mon, 03 Jul 2023 09:12:44 GMT

I am new to Stratus HLS and I use the examples for ramp up my study.

I found that the three simple_dmac_apb/axi/axi_lite are not working out of the box, while some of the lab_* works fine.

Is that expected or is it those non-lab examples need user input in order to work?

I could find little in search engines, so is it easy to get support on this tool?

(FYI I used Catapult/Vivado HLS before and know the basics).

Innovus

polot12 — Tue, 11 Apr 2023 13:59:59 GMT

My innovus simulation result is giving me

ERROR: (IMPSYC-300): Cell Eight_Bit_Adder_Structural_VHDL not found.
ERROR: (IMPVL-904): Can't set top cell to "Eight_Bit_Adder_Structural_VHDL" because it does not exist. Exiting!

How can I solve this error

How to generate Verilog Library with verilog submodules in Stratus?

Saya Lee — Mon, 26 Sep 2022 05:08:09 GMT

Hi!

I'm doing co-sim in Stratus which has a struct that involves both the Generated Verilog and also the imported Verilog modules.

I generated the verilog library used the command like below:

>> bdw_import_verilog -hls_lib "./my_hls_lib/" -clocks "clk" -resets "rst_n" -vfiles "top.sv sub1.sv sub2.sv"

where: the sub1.sv and the sub2.sv are the submodules of top.sv. But if I use this library in the co-sim project, the error below had been came out:

>> xmelab: *E,CUVMUR (top.sv,72|15): instance 'sc_main.system.m_xxxx.xxxx.xxxx0@xxxx<module>.top@top<module>.i_sub1' of design unit 'r_y_top' is unresolved in 'V.sub1:sv'.

>> xmelab: *E,CUVMUR (top.sv,72|15): instance 'sc_main.system.m_xxxx.xxxx.xxxx0@xxxx<module>.top@top<module>.i_sub2' of design unit 'r_y_top' is unresolved in 'V.sub2:sv'.

Now I have to write the sub1 and sub2 modules into top.sv to make the co-sim work. But this is not convenient.

So how to generate the verilog library with top and also submodules in separated .sv files?

Looking forward to your reply.

Thanks!

How to launch Stratus GUI

gdnagendra — Thu, 21 Oct 2021 20:02:52 GMT

Hi, this is a silly first-timer question: when I launch Stratus, I get the command-line version. But I would like to start the GUI version. Tried "stratus --gui" etc but no luck.

Also tried genus-style "raise_gui" command but that didn't work either.

Thanks

Nagendra

Keep tie cells connection

zxw109 — Fri, 17 Sep 2021 16:56:08 GMT

In order to make the later ECO easier, in our design we put in a few constant values driven by tie (high or low) cells. These valuses can easily be changed in case we need to modify them. Genus would optimize the design and won't use the output of the tie cells. How can we keep the connection between the tie cells and their loads?

Syhthesizing bluespec verilog (.bsv) code with Cadence Genus

iamKarthikBK — Mon, 30 Aug 2021 06:49:17 GMT

I want to synthesize some flavor of RISC-V, but I only have the core in Bluespec Verilog (or Bluespec systemverilog ?) ( gitlab.com/.../chromite )
How do I proceed? Can Genus directly read these in Legacy UI with read_hdl?

I have a custom-designed standard cell library characterized using liberate.

Thank you for your time in advance!

Cadence genus Initialisation

rez101998 — Mon, 21 Jun 2021 13:53:03 GMT

Hi,

Could someone please help me resolve this error :
Error : The init design flow needs to be initialized in a proper sequence. The sequence of initialization is as follow.
uninitialized - timing_initialized - physical_initialized - design_initialized - power_initialized - initialization_complete.
[TUI-340] [read_physical]
Cannot perform initialization step 'physical_initialized' from current state 'uninitialized'. Please check and correct your initialization steps.

convert .lib library file to .db file

HaolinCong — Tue, 08 Jun 2021 18:56:38 GMT

Hi,

Is there a way to convert the .lib file to .db file using cadence, like the library_compiler" provided by synopsys?

Thank you very much,

How to change font size for help/menus ?

pmuld0x — Thu, 11 Feb 2021 16:06:26 GMT

Hi,

I am trying to improve reading the menus and the help documents in KDE for Stratus.

Do you have any help on this?

Maybe there is a setting for KDE or with Xwindows fonts file somewhere but I am puzzled.

Thanks for your help!

How to get full module names in report_area command

SrikanthReddy — Sat, 10 Oct 2020 20:00:24 GMT

When I use report_area command in GENUS tool it is shrinking my module name to 115 characters. I want full module name in the report. Please help me to find the full name of module.

Why does Stratus HLS report this error?

idwwwoqq808 — Thu, 03 Sep 2020 05:18:59 GMT

I'm trying to implement a module that reads and writes a memory. The memory is instantiated in the top module and passed down to submodules.

It seems there are errors in the generated memory header file.

I'm using Stratus 19.1 on CentOS 7. I've tried synthesizing "Lab 3: Explicit Memorys" (which comes with Stratus) and it was completed without errors.

Can anyone tell me what the cause of this error and how to solve it?

Also, the way I instantiate memories is same as in Lab3.

I'd prefer to keep ports of memories the same because in the project I'm working on, one module only writes to a memory block and another module only reads from this memory. They will access the same memory simultaneously so I'd rather not to use a shared interface.

Here's the setting of the memory:

And Here's my code:

/* Test3.h */
#include "cynw_p2p.h"
#include "memlib.h"
#include "writer_wrap.h"
#include "reader_wrap.h"

SC_MODULE(Test3)
{
public:
sc_in < sc_uint<8> > din;
sc_out< sc_uint<8> > dout;

// Declaration of clock and reset parameters
sc_in_clk clk;
sc_in < bool > rst;

sc_signal< bool > sgn;

//sc_uint<8> mem[256];
RAM8x256::wrapper< CYN::TLM > *mem;

writer_wrapper m_writer;
reader_wrapper m_reader;

SC_CTOR(Test3)
: m_writer("writer"),
m_reader("reader"),
clk( "clk" ),
rst( "rst" )
{
m_writer.clk(clk);
m_writer.rst(rst);
m_writer.din(din);
m_writer.sgn(sgn);

m_reader.clk(clk);
m_reader.rst(rst);
m_reader.dout(dout);
m_reader.sgn(sgn);

mem = new RAM8x256::wrapper< CYN::TLM > ("mem");
m_writer.m_mem(*mem);
m_reader.m_mem(*mem);
mem->clk_rst(clk,rst);
}
};
//-------------------------------------------------------
/* writer.h */
#include "cynw_p2p.h"
#include "memlib.h"

SC_MODULE(writer)
{
public:
sc_in < sc_uint<8> > din;
sc_out< bool > sgn;

// Declaration of clock and reset parameters
sc_in_clk clk;
sc_in < bool > rst;

//sc_uint<8> *m_mem;
RAM8x256::port_1< CYN::TLM > m_mem;
sc_uint<8> ad;

//SC_HAS_PROCESS(writer);

//writer(sc_module_name &name,
// sc_uint<8> mem[256])
// :m_mem(mem)
SC_CTOR(writer)
{
SC_CTHREAD(writer_thread, clk.pos());
async_reset_signal_is(rst,0);

//HLS_MAP_TO_MEMORY(m_mem,"RAM8x256");
}
void writer_thread();
};
//-------------------------------------------------------
/* writer.cpp */
#include "writer.h"

// The thread function for the design
void writer::writer_thread()
{
// Reset the interfaces
{
CYN_PROTOCOL("writer_thread");

sgn.write(0);
ad=0;
//m_mem.reset();
wait();

// Main execution loop
while (1)
{
m_mem[ad]=din.read();
sgn.write(din.read()[7]);
ad++;
wait();
}
}
}
//-------------------------------------------------------
/* reader.h */
#include "cynw_p2p.h"
#include "memlib.h"

SC_MODULE(reader)
{
public:
sc_in < bool > sgn;
sc_out< sc_uint<8> > dout;

// Declaration of clock and reset parameters
sc_in_clk clk;
sc_in < bool > rst;

sc_uint<8> ad;
sc_uint<8> out_tmp;
//sc_uint<8> (&m_mem)[256];
RAM8x256::port_2< CYN::TLM > m_mem;

//SC_HAS_PROCESS(reader);
//reader(sc_module_name &name,
// sc_uint<8> (&mem)[256])
// :m_mem(mem)
SC_CTOR(reader)
{
SC_CTHREAD(reader_thread, clk.pos());
async_reset_signal_is(rst,0);

//HLS_MAP_TO_MEMORY(m_mem,"RAM8x256");
}
void reader_thread();

};
//-------------------------------------------------------
/* reader.cpp */
#include "reader.h"

// The thread function for the design
void reader::reader_thread()
{
// Reset the interfaces
{
CYN_PROTOCOL("reader_thread");

ad=0;
//m_mem.reset();

wait();

// Main execution loop
while (1)
{
out_tmp=m_mem[ad];

if(sgn.read()){
dout.write( (~out_tmp)+1 );
}else{
dout.write(out_tmp);
}
wait();

ad++;
wait();
}
}
}
//-------------------------------------------------------
The "Job Trace" reports:
00148: Normalization and optimization:
NOTE 00860: Long int data types are being implemented with 64 bits.
02923: Dissolving function boundaries.
02924: Dissolved 198 function calls.
#################################################################
# #
ERROR 03144:# at memlib/c_parts/RAM8x256.h line 3175 #
ERROR 03144.# Call to unresolved virtual function or function called via #
ERROR 03144.# pointer #
# #
#################################################################
#################################################################
# #
FATAL 02368:# at writer.h line 8 #
FATAL 02368.# Not all sc_port->sc_interface bindings and virtual function #
FATAL 02368.# calls could be resolved #
# #
#################################################################

01445: Summary of messages of severity WARNING or greater:
01193: SEVERITY MSGID CNT
01198: FATAL 02368 1
01198: ERROR 03144 1

stratus_hls failed with 2 errors and 0 warnings.

Using Cadence Genus withou any libraries

vinayelk — Fri, 06 Mar 2020 18:24:56 GMT

Hi,

I am fairly new using Cadence Genus but I want to obtain an RTL synthesis from Genus without any library file or just some generic-library.

Is this possible in anyway?

I am sourcing the following tcl file but I dont have any libraries available with me.

#set_attribute lib_search_path /eng/ee/analog-TSMC/tsmc_65_rf

#set_attribute library { low.lib fast.lib}

read_hdl halfadder.v

#elaborate

synthesize -to_generic
#synthesize -to_mapped

write -mapped > halfadder_synth.v

wrtie_script > script

gui_show;
~

Genus Synthesis Timing Report does not make any sense

saw235 — Fri, 03 Jan 2020 17:41:54 GMT

I don't understand how timings are calculated in genus. Below is the synthesis timing report of one of my design, it mentions that critical path is met with 0 slack but the calculation does not make any sense to me because the datapath is 567 ps and the capture time is at 350 ps. So how is it that the timing is met? Usually there are some kind of negative slack if the timing is not met.

There seems to be some ambiguity going on here when one flop is launched at rising edge and captured at the falling edge.

I am targeting 1 GHz, hence target clock period is constrained to 1000ps.

============================================================
Generated by: Genus(TM) Synthesis Solution 17.20-p003_1
Generated on: Jan 03 2020 05:55:41 pm
Module: top
Operating conditions: TT_0P80V_0P00V_0P00V_0P00V_25C (balanced_tree)
Wireload mode: enclosed
Area mode: timing library
============================================================

Path 1: MET (0 ps)
Group: l2clk
Startpoint: (R) lsu_stbuf/stbuf_fwdbyteen_lo_dc3ff_dout_reg[1]/CLK
Clock: (R) l2clk
Endpoint: (R) dec_decode_illegal_any_ff_clkhdr_clkhdr_en_ff_reg/D
Clock: (F) l2clk

Capture Launch
Clock Edge:+ 500 0
Src Latency:+ 0 0
Net Latency:+ 0 (I) 0 (I)
Arrival:= 500 0

Uncertainty:- 150
Required Time:= 350
Launch Clock:- 0
Data Path:- 567
Slack:= 0

High level synthesis

techbud — Thu, 12 Sep 2019 11:49:13 GMT

I've written hobbyist-level Verilog for about 10 years. I'd still consider my understanding of the industry to be mid-level, even a little bit less than that. The more I learn, the more I realize I don't know about. YMMV.

I'm adverse to the going above the RTL/HDL level of languages. My main concern is that you're essentially compiling/transpiling/outputting to HDL from a completely different procedural top-down sequential programming language. These languages use a series of steps, where the CPU is executing the first line of code, the next line, the one following, and so on. You're not describing what hardware to instantiate or build, you're telling the CPU what to do step by step by step. There's some minor differences with how OOP relates, but it still closely mimics the fetch-decode-execution cycle of the underlying hardware. Sure C#/.NET or Java gets compiled down to some byte-code, run within some *VM, and then essentially converted to assembly language. The point is that you're going SAME-SAME during the whole process.

Javascript transpilers are the same -- take some flavor of javascript in, put some flavor of javascript out. This works because it's same-same.

You have to understand digital design before you can start writing in HDLs. The hard part about using Verilog, from my experience, isn't the syntax problem of "How do I do xyz in Verilog?" but "What hardware am I trying to describe?" With full view and understanding of what happens to each of your modules during a clock tick. Sure, there's still an idea of "this set of code executes whenever this happens", but there's some serious problems regarding the simultaneous nature of hardware. Very little happens simultaneously in a CPU --- even though it may execute it fast enough for you to believe it's happening at the same time.

Synthesize net to flip-flop cell with differential output.

RemyP — Sat, 22 Jun 2019 22:47:22 GMT

I have a digital block (SystemVerilog) that will eventually be placed into a larger AoT design. The connections between the analog and digital blocks need to be differential due to noise issues. I created a D flip-flop standard cell with a differential output (Q, nQ) that meets all the timing requirements of this design. This was characterized using Liberate and is now in the library I am using in Genus for synthesis.

Is it possible to configure Genus to synthesize specific output nets (by name) to this flip flop so that both Q and nQ are available in Innovus for P&R? If so, a link to the appropriate manual or documentation would be most appreciated - searching on the Cadence website hasn't revealed anything immediately useful.

Our previous method was to explicitly create both outputs in the HDL source and use HDL logic to ensure they were differential. This caused an additional inverter to be placed into the design which had a negative impact on timing. This method obviously does not scale to large designs and is somewhat bug-prone. Any better method would be appreciated.

Thanks for your help in advance!

The cell definition used in Liberate to generate the flip flop during characterization is shown below. It doesn't seem like Liberate is aware that Q and nQ are logically related but I was unable to find any option to define_cell that would achieve this.

set cell DFFC
if {[ALAPI_active_cell $cell]} {
    define_cell \
       -clock { CLK } \
       -async { nCLR } \
       -input { D } \
       -output { Q nQ } \
       -pinlist { CLK nCLR D Q nQ } \
       -delay delay_template \
       -power power_template \
       -constraint const_template \
       $cell
}

Stratus PnR Configs

kvasa — Mon, 20 May 2019 12:14:24 GMT

I browsed through the User Guide and other online support materials but couldn't find how to define a PNR config. Kindly help me with the same.

Genus - Segmentation Fault

nokta — Wed, 03 Oct 2018 10:38:28 GMT

Hello everyone,
I am trying to do large-scale Genus RTL synthesis in our new server. But I get Segmentation Fault while doing that. At above you can see the end of my genus.log file. I change information where I write something between <>

Removing temporary intermediate hierarchies under pbs_gen_n_7
Sourcing './.pbs_<server address>_110854/pbs_gen_n_7.etf' (<data and time>)...
rdbfname wdbfname effort physical pas design assembly_index
./.pbs_<server address>_110854/pbs_gen_n_7.db ./.pbs_<server address>_110854/pbs_gen_n_7_post.db medium 0 0 /designs/pbs_gen_n_7 -1

Segmentation Fault accessing address ffffffffffffc6a0.

Fatal internal error, code 11 (Segmentation fault)

Dumping stack trace (tid:7fdf8e241500/main thread).

Operating System: linux
Product Version: 17.11-s014_1
Build Date: Oct 9 2017
Executable: <cds dir>/GENUS171/tools.lnx86/synth/bin/64bit/genus
Startup Options: -legacy_ui
Current Directory: <my dir>
Stack trace:

Do you have any idea for this situation?
Thank you

set_multicycle_path using clock enable signals

Hildebrandt — Tue, 12 Jun 2018 09:46:10 GMT

Hello!

For synthesis with Genus 17.1 I want to constrain a multi-cycle path inside one single clock domain from some flipflops using one clock enable signal to some other flipflops using a different clock enable signal. There is a solution for Altera Quartus <https://www.altera.com/support/support-resources/design-examples/design-software/timinganalyzer/exm-tq-clock-enable.html>, which works fine for Quartus, but not for Genus. After adapting the syntax of the Quartus solution I tried in Genus:

set_multicycle_path 4 -from [get_fanout [get_pins my_component/my_clock_enable_1_reg/q]] -to [get_fanout [get_pins my_component/my_clock_enable_2_reg/q]] -setup

but the <get_fanout> command gives a list, which includes objects, which are not supported by <set_multicycle_path>. Here is the relevant part of the error message:

Error : A given object is not suitable for this exception. [SDC-211] [set_multicycle_path]
: The 'set_multicycle_path' command does not allow '-from' specifications for pins on unmapped combinational or hierachical instances ...

The used clock-enable signals are used inside clocked processes as combinational logic and together with other combinational conditions the synthesis tool recognizes this as clock-enable. Here is the pseudo-code:

elsif rising_edge(clk) then

if (clock_enable_1='1' AND other_condition='1') then

Ralf

(Cadence Genus Synthesis) How to use more than one library file for synthesis?

Raveen Kumar — Fri, 13 Apr 2018 12:29:55 GMT

Below is my Genus synthesis script.tcl,

    #Script

    #Setting Library and Design Path
    set_attribute lib_search_path ../lib/

    set_attribute hdl_search_path ../design_files/

    #Setting Library and Design Files
    set_attribute library tech1.lib

    #Analyze and Elaborate the Design File
    read_hdl -sv count.sv
    elaborate

    # Apply Constraints and generate clocks
    read_sdc ../constraints/constraints.sdc

    # Synthesize the design to the target library
    synthesize -to_mapped -effort medium

    # Write out the reports
    report timing > count_timing.rep
    report gates  > count_cell.rep
    report power  > count_power.rep

    # Write out the structural Verilog and sdc files
    write_hdl > count_netlist.v
    write_sdc > count_sdc.sdc

How to write a script to import multiple library files say, tech1.lib, tech2.lib,... and synthesize the design with each and everone of them and generate reports? Also is there an option to make the tool to report best library to match timings of the design.

Thanks.

Synthesis Area plus power estimate concatenation

GioFz — Wed, 07 Feb 2018 17:59:24 GMT

Hello guys,

I am currently working on a project where I synthetize thousands of small little combinatorial blocks. These blocks are similar and my purpose it is to find simply the best one for AREA and POWER. My current genus/rc script can do this easily for the AREA but I am struggling to find an efficient way to do the same with the power.
My current script is the following:

***********************CODE**********************************

set_attribute information_level 2
set_attribute lib_search_path ../../libs
set_attribute library gf40.lib

read_hdl -sv -library WORK ../vlog/blocks0001.v

set DESIGN block0001000

elaborate $DESIGN
check_design -unresolved $DESIGN

set input_port_list { a }
set output_port_list { y }

synthesize -to_generic -effort high $DESIGN
synthesize -to_mapped -effort high $DESIGN

set area_design [get_attribute area $DESIGN]
set out [open "../rpt/blocks0001.rpt" w]
puts $out "Total gate_count $DESIGN : $area_design"
close $out

read_hdl -sv -library WORK ../vlog/blocks0001.v

set DESIGN block0001001

elaborate $DESIGN
check_design -unresolved $DESIGN

set input_port_list { a }
set output_port_list { y }

synthesize -to_generic -effort high $DESIGN
synthesize -to_mapped -effort high $DESIGN

set area_design [get_attribute area $DESIGN]
set out [open "../rpt/blocks0001.rpt" a]
puts $out "Total gate_count $DESIGN : $area_design"
close $out

.... and so on

****************************************************************

It compiles the verilog codes from one only generated file. The result is this:

***********************RESULT*****************************

Total gate_count block0001000 : 18.522
Total gate_count block0001001 : 18.522
Total gate_count block0001002 : 18.8748
Total gate_count block0001003 : 18.8748
Total gate_count block0001004 : 13.7592
Total gate_count block0001005 : 12.5244
Total gate_count block0001006 : 19.0512..... so on

**************************************************************

So all Area estimations are in the same report, very easily extractable. For the power I tried to the same with report_power and report_gates -power commands, but I cannot get any good result.
Do you have any suggestion about this?

P.S.
I am quite new with the cadence softwares so I know my question could sound a little bit silly and imprecise, so please ask for more details if you need it.

Domino Logic Synthesis using Genus

Schriek — Mon, 22 Jan 2018 16:35:49 GMT

Hi,

I've created two sets of standard cells, static and dynamic (or domino), consisting of basic combinational gates and some sequential elements.
Using Genus, I am using the library domains functionality to map some behavioral HDL (i.e. multiplier) to both the static and the domino gates.
The static version maps just fine, the domino gates however, are not recognized as usable gates.

The specific error message is:

At least one usable two-input and/or/nand/nor gate (modulo inversion at inputs) is required for mapping.
Ensure that the loaded libraries contain at least one such cell. [LBR-172]

Both an OR and AND domino gate are available.
I figured, since the domino gates have three inputs, Genus does not recognize them as usable basic gates.
Hence the question, is it even possible to map to these domino gates using Genus and if so, how to do so?

Thanks.

inserting scan chain - DFT

subashrajam — Tue, 23 May 2017 06:31:03 GMT

Could you help to insert the scan chain in RTL design by providing the required script file?