High-Level Synthesis - Recent Threads

To add asynch. reset at Stratus example-1

SC202501247228 — Tue, 11 Feb 2025 01:11:16 GMT

Hi I'm newbie in HLS

For stratus example-1, I have one question.

I expected that I could add async. reset for all f/f/ but I couldn't add at the output data registers while all other f/fs were synthesized with async. reset.

What I changed was

SC_CTOR( dut )

{

SC_CTREAD( thread_function, clk.pos() );

reset_singal_is( rst, 0 ); --> async_reset_signal_is( rst, 0 );

din.clk_rst( clk, rst ); --> din.clk_rst_async( clk, rst );

dout.clk_rst( clk, rst ); --> dout.clk_rst_async( clk, rst, false);

}

All synthesized f/fs except output data f/f have async. reset.

f/f with async. reset : always_ff( posedge clk or negedge rst)

output data f/f : always_ff(posedge clk)

So what I missed ?

find cells in row next to all same

zehtr — Mon, 25 Sep 2023 02:30:21 GMT

I have special capacitor cells in layout. sometimes they abut next to each other in cell row. Need to find all the places where there are many of these next to. When find them,get the X1 X2 of where they are in a row. How to complete task?

write placement blockage around cell

zehtr — Mon, 25 Sep 2023 02:26:07 GMT

I have special placed cell. I need to find cell and draw placement blockage for full width of cell for the complete height of the design. From top to bottom of the design. How to complete task?

Delivered example STRATUS_20.24.100/share/stratus/collateral/examples/simple_dmac_apb is not able to work.

mxlusereight — Mon, 03 Jul 2023 09:12:44 GMT

I am new to Stratus HLS and I use the examples for ramp up my study.

I found that the three simple_dmac_apb/axi/axi_lite are not working out of the box, while some of the lab_* works fine.

Is that expected or is it those non-lab examples need user input in order to work?

I could find little in search engines, so is it easy to get support on this tool?

(FYI I used Catapult/Vivado HLS before and know the basics).

Innovus

polot12 — Tue, 11 Apr 2023 13:59:59 GMT

My innovus simulation result is giving me

ERROR: (IMPSYC-300): Cell Eight_Bit_Adder_Structural_VHDL not found.
ERROR: (IMPVL-904): Can't set top cell to "Eight_Bit_Adder_Structural_VHDL" because it does not exist. Exiting!

How can I solve this error

How to generate Verilog Library with verilog submodules in Stratus?

Saya Lee — Mon, 26 Sep 2022 05:08:09 GMT

Hi!

I'm doing co-sim in Stratus which has a struct that involves both the Generated Verilog and also the imported Verilog modules.

I generated the verilog library used the command like below:

>> bdw_import_verilog -hls_lib "./my_hls_lib/" -clocks "clk" -resets "rst_n" -vfiles "top.sv sub1.sv sub2.sv"

where: the sub1.sv and the sub2.sv are the submodules of top.sv. But if I use this library in the co-sim project, the error below had been came out:

>> xmelab: *E,CUVMUR (top.sv,72|15): instance 'sc_main.system.m_xxxx.xxxx.xxxx0@xxxx<module>.top@top<module>.i_sub1' of design unit 'r_y_top' is unresolved in 'V.sub1:sv'.

>> xmelab: *E,CUVMUR (top.sv,72|15): instance 'sc_main.system.m_xxxx.xxxx.xxxx0@xxxx<module>.top@top<module>.i_sub2' of design unit 'r_y_top' is unresolved in 'V.sub2:sv'.

Now I have to write the sub1 and sub2 modules into top.sv to make the co-sim work. But this is not convenient.

So how to generate the verilog library with top and also submodules in separated .sv files?

Looking forward to your reply.

Thanks!

RE: Cá độ Liên Minh Huyền Thoại ở đâu uy tín?

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How to launch Stratus GUI

gdnagendra — Thu, 21 Oct 2021 20:02:52 GMT

Hi, this is a silly first-timer question: when I launch Stratus, I get the command-line version. But I would like to start the GUI version. Tried "stratus --gui" etc but no luck.

Also tried genus-style "raise_gui" command but that didn't work either.

Thanks

Nagendra

Keep tie cells connection

zxw109 — Fri, 17 Sep 2021 16:56:08 GMT

In order to make the later ECO easier, in our design we put in a few constant values driven by tie (high or low) cells. These valuses can easily be changed in case we need to modify them. Genus would optimize the design and won't use the output of the tie cells. How can we keep the connection between the tie cells and their loads?

Syhthesizing bluespec verilog (.bsv) code with Cadence Genus

iamKarthikBK — Mon, 30 Aug 2021 06:49:17 GMT

I want to synthesize some flavor of RISC-V, but I only have the core in Bluespec Verilog (or Bluespec systemverilog ?) ( gitlab.com/.../chromite )
How do I proceed? Can Genus directly read these in Legacy UI with read_hdl?

I have a custom-designed standard cell library characterized using liberate.

Thank you for your time in advance!

Why does Stratus HLS report this error?

idwwwoqq808 — Thu, 03 Sep 2020 05:18:59 GMT

I'm trying to implement a module that reads and writes a memory. The memory is instantiated in the top module and passed down to submodules.

It seems there are errors in the generated memory header file.

I'm using Stratus 19.1 on CentOS 7. I've tried synthesizing "Lab 3: Explicit Memorys" (which comes with Stratus) and it was completed without errors.

Can anyone tell me what the cause of this error and how to solve it?

Also, the way I instantiate memories is same as in Lab3.

I'd prefer to keep ports of memories the same because in the project I'm working on, one module only writes to a memory block and another module only reads from this memory. They will access the same memory simultaneously so I'd rather not to use a shared interface.

Here's the setting of the memory:

And Here's my code:

/* Test3.h */
#include "cynw_p2p.h"
#include "memlib.h"
#include "writer_wrap.h"
#include "reader_wrap.h"

SC_MODULE(Test3)
{
public:
sc_in < sc_uint<8> > din;
sc_out< sc_uint<8> > dout;

// Declaration of clock and reset parameters
sc_in_clk clk;
sc_in < bool > rst;

sc_signal< bool > sgn;

//sc_uint<8> mem[256];
RAM8x256::wrapper< CYN::TLM > *mem;

writer_wrapper m_writer;
reader_wrapper m_reader;

SC_CTOR(Test3)
: m_writer("writer"),
m_reader("reader"),
clk( "clk" ),
rst( "rst" )
{
m_writer.clk(clk);
m_writer.rst(rst);
m_writer.din(din);
m_writer.sgn(sgn);

m_reader.clk(clk);
m_reader.rst(rst);
m_reader.dout(dout);
m_reader.sgn(sgn);

mem = new RAM8x256::wrapper< CYN::TLM > ("mem");
m_writer.m_mem(*mem);
m_reader.m_mem(*mem);
mem->clk_rst(clk,rst);
}
};
//-------------------------------------------------------
/* writer.h */
#include "cynw_p2p.h"
#include "memlib.h"

SC_MODULE(writer)
{
public:
sc_in < sc_uint<8> > din;
sc_out< bool > sgn;

// Declaration of clock and reset parameters
sc_in_clk clk;
sc_in < bool > rst;

//sc_uint<8> *m_mem;
RAM8x256::port_1< CYN::TLM > m_mem;
sc_uint<8> ad;

//SC_HAS_PROCESS(writer);

//writer(sc_module_name &name,
// sc_uint<8> mem[256])
// :m_mem(mem)
SC_CTOR(writer)
{
SC_CTHREAD(writer_thread, clk.pos());
async_reset_signal_is(rst,0);

//HLS_MAP_TO_MEMORY(m_mem,"RAM8x256");
}
void writer_thread();
};
//-------------------------------------------------------
/* writer.cpp */
#include "writer.h"

// The thread function for the design
void writer::writer_thread()
{
// Reset the interfaces
{
CYN_PROTOCOL("writer_thread");

sgn.write(0);
ad=0;
//m_mem.reset();
wait();

// Main execution loop
while (1)
{
m_mem[ad]=din.read();
sgn.write(din.read()[7]);
ad++;
wait();
}
}
}
//-------------------------------------------------------
/* reader.h */
#include "cynw_p2p.h"
#include "memlib.h"

SC_MODULE(reader)
{
public:
sc_in < bool > sgn;
sc_out< sc_uint<8> > dout;

// Declaration of clock and reset parameters
sc_in_clk clk;
sc_in < bool > rst;

sc_uint<8> ad;
sc_uint<8> out_tmp;
//sc_uint<8> (&m_mem)[256];
RAM8x256::port_2< CYN::TLM > m_mem;

//SC_HAS_PROCESS(reader);
//reader(sc_module_name &name,
// sc_uint<8> (&mem)[256])
// :m_mem(mem)
SC_CTOR(reader)
{
SC_CTHREAD(reader_thread, clk.pos());
async_reset_signal_is(rst,0);

//HLS_MAP_TO_MEMORY(m_mem,"RAM8x256");
}
void reader_thread();

};
//-------------------------------------------------------
/* reader.cpp */
#include "reader.h"

// The thread function for the design
void reader::reader_thread()
{
// Reset the interfaces
{
CYN_PROTOCOL("reader_thread");

ad=0;
//m_mem.reset();

wait();

// Main execution loop
while (1)
{
out_tmp=m_mem[ad];

if(sgn.read()){
dout.write( (~out_tmp)+1 );
}else{
dout.write(out_tmp);
}
wait();

ad++;
wait();
}
}
}
//-------------------------------------------------------
The "Job Trace" reports:
00148: Normalization and optimization:
NOTE 00860: Long int data types are being implemented with 64 bits.
02923: Dissolving function boundaries.
02924: Dissolved 198 function calls.
#################################################################
# #
ERROR 03144:# at memlib/c_parts/RAM8x256.h line 3175 #
ERROR 03144.# Call to unresolved virtual function or function called via #
ERROR 03144.# pointer #
# #
#################################################################
#################################################################
# #
FATAL 02368:# at writer.h line 8 #
FATAL 02368.# Not all sc_port->sc_interface bindings and virtual function #
FATAL 02368.# calls could be resolved #
# #
#################################################################

01445: Summary of messages of severity WARNING or greater:
01193: SEVERITY MSGID CNT
01198: FATAL 02368 1
01198: ERROR 03144 1

stratus_hls failed with 2 errors and 0 warnings.

RE: Why does Stratus HLS report this error?

Rosemary — Fri, 13 Aug 2021 17:26:49 GMT

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Cadence genus Initialisation

rez101998 — Mon, 21 Jun 2021 13:53:03 GMT

Hi,

Could someone please help me resolve this error :
Error : The init design flow needs to be initialized in a proper sequence. The sequence of initialization is as follow.
uninitialized - timing_initialized - physical_initialized - design_initialized - power_initialized - initialization_complete.
[TUI-340] [read_physical]
Cannot perform initialization step 'physical_initialized' from current state 'uninitialized'. Please check and correct your initialization steps.

RE: Why does Stratus HLS report this error?

jimmashyeg — Wed, 16 Jun 2021 06:12:42 GMT

I'm trying to implement a module that reads and writes a memory. The memory is instantiated in the top module and The tutorial, instead, will not explore the capabilities of the HLS tool for design-space exploration. ... accelerator name [dummy]: mac * Select design flow (Stratus HLS, ... configured by the accelerator initialization script is reported below. ... jouets et figurines à https://figurinestore.fr/ In case of simulation errors during the RTL simulation that do not ......

convert .lib library file to .db file

HaolinCong — Tue, 08 Jun 2021 18:56:38 GMT

Hi,

Is there a way to convert the .lib file to .db file using cadence, like the library_compiler" provided by synopsys?

Thank you very much,

How to change font size for help/menus ?

pmuld0x — Thu, 11 Feb 2021 16:06:26 GMT

Hi,

I am trying to improve reading the menus and the help documents in KDE for Stratus.

Do you have any help on this?

Maybe there is a setting for KDE or with Xwindows fonts file somewhere but I am puzzled.

Thanks for your help!

How to get full module names in report_area command

SrikanthReddy — Sat, 10 Oct 2020 20:00:24 GMT

When I use report_area command in GENUS tool it is shrinking my module name to 115 characters. I want full module name in the report. Please help me to find the full name of module.

Domino Logic Synthesis using Genus

Schriek — Mon, 22 Jan 2018 16:35:49 GMT

Hi,

I've created two sets of standard cells, static and dynamic (or domino), consisting of basic combinational gates and some sequential elements.
Using Genus, I am using the library domains functionality to map some behavioral HDL (i.e. multiplier) to both the static and the domino gates.
The static version maps just fine, the domino gates however, are not recognized as usable gates.

The specific error message is:

At least one usable two-input and/or/nand/nor gate (modulo inversion at inputs) is required for mapping.
Ensure that the loaded libraries contain at least one such cell. [LBR-172]

Both an OR and AND domino gate are available.
I figured, since the domino gates have three inputs, Genus does not recognize them as usable basic gates.
Hence the question, is it even possible to map to these domino gates using Genus and if so, how to do so?

Thanks.

RE: Domino Logic Synthesis using Genus

jason34 — Thu, 13 Aug 2020 11:39:16 GMT

[deleted]

Using Cadence Genus withou any libraries

vinayelk — Fri, 06 Mar 2020 18:24:56 GMT

Hi,

I am fairly new using Cadence Genus but I want to obtain an RTL synthesis from Genus without any library file or just some generic-library.

Is this possible in anyway?

I am sourcing the following tcl file but I dont have any libraries available with me.

#set_attribute lib_search_path /eng/ee/analog-TSMC/tsmc_65_rf

#set_attribute library { low.lib fast.lib}

read_hdl halfadder.v

#elaborate

synthesize -to_generic
#synthesize -to_mapped

write -mapped > halfadder_synth.v

wrtie_script > script

gui_show;
~