Chiplet Interface for Heterogeneous SiP

Offline binary1010 1 month ago

https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/cowos-info

I came across cadence old article that discussing about TSMC advance packaging technology such as InFO & CoWoS. However, I couldn’t find information such as what I/O interface standard is required to realize this multi-chip SiP. For example, Intel using their proprietary AIB interface for EMIB solution.

Besides, any idea if inFO also able to supports multi-chip integration for older node process to new node process such as 40-nm to 16-nm?

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Chiplet Interface for Heterogeneous SiP

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