Implementation - Recent Threads

cdb2oa translator

RM202605273230 — Mon, 01 Jun 2026 07:09:44 GMT

Hi,

I am trying to import a TSMC 65nm standard cell library, and I noticed that the library files are in the legacy CDB format, whereas my current Cadence Virtuoso installation uses the OpenAccess (.oa) database format.

I attempted to use the CDB-to-OA translator (cdb2oa), but it appears that the translator is either not available in my installation or has been removed. I also tried enabling it through the available Cadence utilities, but I encountered issues that seem to be related to version compatibility.

Could you please provide guidance on the following:

Which Cadence Virtuoso versions support the cdb2oa translator?
What are the compatibility requirements between the source CDB library and the target OA/Virtuoso version?
How can I verify whether the cdb2oa translator is installed in my environment?
If it is not installed, what is the recommended procedure to obtain and install it?
Are there any required licenses, environment variables, or setup steps needed before running the translator?
Could you share any official documentation, installation guides, or reference resources related to the CDB-to-OA migration process?

Any details regarding supported versions, installation procedures, and usage examples would be greatly appreciated.

Thank you for your assistance.

Best regards,
Mohammed Rafeeq Khan

How to get Xtensa SDK license for build

ES202507032019 — Mon, 21 Jul 2025 05:36:45 GMT

Hello everyone,

I am currently working on a project that requires the use of the Cadence Xtensa SDK Xplorer-9.0.17-linux-x64-installer, and I need to obtain a license for it. I was wondering if anyone here could guide me through the process of acquiring a license for this SDK.

Here are a few specific questions I have:

Where can I purchase the license? - Is there a specific website or contact person I should reach out to for purchasing the license?
What types of licenses are available? - Are there different types of licenses (e.g., academic, commercial) and what are the differences between them?
What is the cost of the license? - Can anyone provide a rough estimate of the cost involved?
Are there any prerequisites or documentation required? - Do I need to provide any specific information or documentation when applying for the license?
How long does it take to obtain the license? - What is the typical processing time from application to receiving the license?
Any additional tips or advice from those who have gone through this process would be greatly appreciated. Thank you in advance for your help!

Setting up host software to interact with firmware in xtensa xplorer

ReisBoiXie — Sat, 27 Apr 2024 00:03:14 GMT

Hi all,

I have implemented the firmware simulator for a customized system configuration. Since it's a message queue based firmware, I'm trying to set up a standalone host software to send/process commands to interact with the firmware simulator. Is there a way to do that within xplorer?

PS. I thought of setting up a multiprocessor system: using one as the "host processor" and the other one as the target firmware processor, but it seems that only certain configurations are compatible with multiprocessor project. I'm using a customized configuration, so seems to be a dead end.

PPS. I have implemented something similar in visual studio, it's basically a multithreading program that starts with the host thread, then firmware thread, then those two threads can interact with each other. But since visual studio simulator cannot provide meaningful profiling result, I'm searching for a similar solution in xplorer.

PNR flow

TrinadhSai — Wed, 17 Apr 2024 08:43:10 GMT

As we don't check for timing during floor plan stage unless it is the engineer concern to check timing, so why do innovus tool won't move forward until timing libraries are read ?

Executable view in xtensa xplorer

1234 Madhu — Fri, 15 Sep 2023 07:51:40 GMT

I installed xtensa xplorer SDK where I built a test suite XOS test application . I loaded the executables to debug and get the code flow , but I am able to see assembly code not the real C code , Is there any way to view the built C code rather than the actual assembly code. Please help

Loading executable to xtensa explorer IDE - for debugging a testsuite application

1234 Madhu — Fri, 15 Sep 2023 06:00:00 GMT

I installed xtensa explorer SDK which has some example application and testsuite for XOS APIs , I tried to build and run the executable in my terminal , I am able to see the output but I want to debug and see the code working using xtensa explorer IDE . Please help me how to debug the code to know the code flow .

PNR using Innovus

AnithaShrey211 — Fri, 04 Mar 2022 06:44:09 GMT

What does this command mean set sprCreateIeRingOffset 1.0 in the power planning stage of pnr ?

PNR command

AnithaShrey211 — Fri, 04 Mar 2022 06:19:28 GMT

Hello, I am new to this forum. While using innovus for pnr, after we invoke innovus I noticed this command in the command window

suppressMessage ENCEXT-2799

what does ENCEXT-2799 mean?

uvm Error-[IND] Identifier not declared

rkaur9 — Fri, 12 Nov 2021 07:17:19 GMT

Hello ,

My code for sequence is follows ,

`ifndef seq_stimulus
`define seq_stimulus

import uvm_pkg::*;
`include "uvm_macros.svh"

class seq_stimulus extends stimulus;

`uvm_object_utils(seq_stimulus)

stimulus req;
function new(string name = "seq_stimulus");
super.new(name);
endfunction

virtual task body();
req = stimulus::type_id::create("req");
`uvm_do(req);
`uvm_info(get_type_name(),$sformatf("data = 'h%0h,valid= 'h%0h",req.data,req.valid),UVM_HIGH)

endtask

endclass

`endif

but it gives error:

Error-[IND] Identifier not declared
/classes_v/seq_stimulus.sv, 20
Identifier 'create_item' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.

Error-[IND] Identifier not declared
seq_stimulus.sv, 20
Identifier 'start_item' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.

Error-[IND] Identifier not declared
seq_stimulus.sv, 20
Identifier 'finish_item' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.

please suggest thnks

pnR problem

soodswar — Wed, 13 Oct 2021 06:05:30 GMT

Hello i am getting errors like this can i ignore or proceed to pnR

Building hierarchical netlist for Cell TMR_SHIFTREG ...
*** Netlist is NOT unique.
Set DBUPerIGU to techSite CORE9T width 180.
** info: there are 874 modules.
** info: there are 141652 stdCell insts.

*** Memory Usage v#1 (Current mem = 1034.156M, initial mem = 295.168M) ***
**WARN: (IMPFP-3961): The techSite 'CORE20T_4V' has no related standard cells in the LEF/OA library. The calculations for this site type cannot be made unless standard cell models of this type exist in the LEF/OA library. Ignore this warning if the SITE is not used by the library. Alternatively, remove the SITE definition for the LEF/OA library to avoid this message.
Type 'man IMPFP-3961' for more detail.

*** Summary of all messages that are not suppressed in this session:
Severity ID Count Summary
WARNING IMPLF-200 3 Pin '%s' in macro '%s' has no ANTENNAGAT...
WARNING IMPFP-3961 29 The techSite '%s' has no related standar...
WARNING TCLCMD-1014 10 The SDC set_operating_conditions asserti...
WARNING TCLCMD-1461 10 Skipped unsupported command: %s
WARNING TECHLIB-302 120 No function defined for cell '%s'. The c...
WARNING TECHLIB-1435 13 For dc_current table defined in cell '%s...
*** Message Summary: 185 warning(s), 0 error(s)

[characterization] how to set up the liberate template?

sherryshe — Sun, 03 Oct 2021 14:09:02 GMT

Hi,

I have some questions while characterizing...

Is index 1 (input transition) rise time?

And how to set up the index 1( input transition) ,index 2(output load) in the template properly since different cells have different sizes and drives?

In the end, how to verify the result from characterization?

importing DEF into virtuoso

sherryshe — Sun, 03 Oct 2021 10:23:30 GMT

Hi, problem again, the metal is normal in innovus, but when I import the DEF into the virtuoso, M2 and M3 automatically routed changed into strings, how can I fix this? the problem came from tech.lef or the settings?😥

Functional coverage: array of covergroups

CK47 — Tue, 14 Sep 2021 19:01:45 GMT

Hi
I need to create a array of cover groups. I declared the covergroup in a class and created a array of classes. I used generate block to instantiate the class.

Once I run the tests to get coverage, the IMC tool shows only one instance of the class and covergroup in functional coverage section. How ever there are multiple instances of this covergroup created in code coverage section.

I need multiple instances of the covergroup in functional coverage section.

Below is the code I used -

class cg_wrapper ;
covergroup cg_test with function sample(bit x);
cp_temp: coverpoint x { bins zero_1 = (0=>1);
bins one_0 = (1=>0);}
endgroup

function new (string name = "cg_temp_w");
cg_test = new();
cg_test.set_inst_name(name);
endfunction

function sample (bit x);
cg_test.sample(x);
endfunction
endclass

genvar kk ;
generate for(kk = 0;kk<9;kk++)
begin : cg_test_wrap
cg_wrapper wrapper_inst = new(temp_bit[kk]);
end
endgenerate

Appending an inst to a schematic with TCL commands in Innovus

MichaelWood — Mon, 19 Jul 2021 22:09:07 GMT

Basically, I'm trying to write a script that will take a list of objects and open a schematic window showing them all. I can do this manually by right-clicking on an inst and selecting the "Schematic View (Cone) -> Append..." option in the dropdown menu, but I haven't been able to figure out how to do it in the terminal window.

With the "gui_get_ui" command, I was able to find this element, called "popupMenu.subopenSchCone.Append...", and it tells me the command it runs is: "RdaObjMenu::openSch append cone 0x<address>". However, if I try to run this myself, I'm told the namespace "RdaObjMenu" doesn't exist. I was hoping someone could shed some light on this situation.

Simulation of OTA with high input range and load drive capacity to obtain design parameters

Maryjos — Sat, 10 Jul 2021 11:25:15 GMT

I want to do some simulations to find design parameters for an OTA .
This is for implementing an OTA based active second order low pass filer, to be used in a high speed wide bandwidth PLL

So the OTA should have:

high output impedance.
should be able to drive a capacitor of about 10-20 pF.
should have a large input range

Are there some ideal models available from which I could find the gain bandwidth product, slew rate and gain? Can someone help me understand what should be the design considerations and how the simulations can be done?