I am synthesizing a vhdl netlist with pacakge declarations .The verilog
o/p netlist has PORT names expanded with record elelents .
Is there a method where port names are output in the verilog as it is "without" the record elements.
type A is record
x:std_logic_vector(15 downto 4);
o/p of verilog netlist is "port_name[x] " ;in [15:0]
what should be dont to get only ---> port_name
I have already tried the following variables;
I may ask a stupid question but why are you using a record, especially in the example you are providing? If you want to synthesize you RTL you need to use only bit (std_logic) and vectors (std_logic_vector), no enumerated types or anything else as it can not be properly represented after synthesis. So my recommendation is that you modify your VHDL so that your interface is not using record and then everything should be well.Eric.