Logic Design Forums

High Level Synthesis

leniejame48
4 days ago

So I’m a senior in computer engineering and currently taking an advanced digital systems design course. My professor has opted the require us to do our labs using high level synthesis as opposed to VHDL like before. My question is if that’s even beneficial to the student? I feel like it will create an abstraction that breaks away from thinking of your design at a hardware level and up to Mobdro a language like C. Maybe I’m wrong, any opinions?VidMate

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.