Genus: Problem with long module name due to parameter types

Hello,

I'm currently synthesizing a SytemVerilog design using Genus 19.11. In the report, I'm getting the information, that there is one subdesign with a long module name. It turned out that this long module name is caused by the fact that the parameters of a module are appended to the module instance name.

To fix that, I set the root attribute hdl_parameter_naming_style to _%d as recommended in the documentation to get rid of the parameter names itself and only append the values. However, this does not apply if a module makes use of parameter types. The name of the parameter type is still appended with the prefix type_, which still causes long names if the design hierarchy is flattened.

Now I have two questions to which I haven't found a solution yet:

1. Is there a attribute I can set to prevent the issue with parameter types and reduce the length of the module name?
2. Is it possible to let Genus automatically rename long module names?

Thank's in advance!