Logic Design - Recent Threads

Timing closure on cloned clock gate enable inputs

YJ202602057834 — Thu, 05 Feb 2026 15:36:13 GMT

Our IP has a software controlled clock gate controlling an entire clock domain (several hundred flops). I noticed that in some cases, the clock gate is cloned post CTS, which create a large fanout path from the enable to the different clones. This path fails then fails timing checks. Apologies if this should not come as a surprise; I'm mostly a Verilog guy.

I have searched quite a lot online but could not find a reliable method of dealing with this kind of problem. The only method that could seemingly solve this is a set_max_fanout/set_register_duplication directive on the enable flop, but for reasons that people online do not explain, backend engineers do not like to use these directives. So:

Is there an industry-standard way to deal with this kind of problems?
Can anyone tell me why set_max_fanout/set_register_duplication directives are frowned upon?

I have some ideas regarding 1 but they usually involve severe limits on the users to configure clock gating only within a reset context.

Many thanks in advance!

RE: Timing closure on cloned clock gate enable inputs

YJ202504163215 — Mon, 09 Mar 2026 21:36:24 GMT

You may want to clone the clock gates during synthesis itself. There you can clone the enable flop as well. That way you see this issue much earlier than waiting until post cts.

Another solution if for any reason it is not duplicated during synthesis you can try to duplicate during prects that is during place_opt_design. You can clone enable flop post syn thesis but it tends to be not on the expected lines. The issue is the logic on the data path is dependent on too many inputs and using the above commands you may have to clone path from all the inputs to allow you to move the combinational cells freely. The tendency of the tool is to place clock gates closer to fanout flops thereby keeping latency on the lower side but the impact is seen on the enable side.

Static power consumption of domino logic and cmos logic AND gate (cadence 6.1.8)

MM202602287655 — Sat, 28 Feb 2026 21:41:16 GMT

I am comparing the performance parametrics of cmos logic and domino logic from room temperature to cryogenic temperature.

I was measuring the parameters like dynamic power consumption, static power, delay etc

Basically I am working both circuits on same schematic cell view with same Vdd, load and input frequency.

firstly i tried measuring static power consumption by shift deleting one circuit at a time in schematic as both had common vdd supply and global ground. At that time cmos has pW range power consumption in room temperature and it reduces only by few to cryogenic. Domino had more static power at room from nW and it went to pW range in cryogenic, but the decrease was not gradual, it was random fluctuating with high and low. Also at some instances it gave negative power.

While giving negative power, how to take the value, should we consider the magnitude at that temperature.

Also later i gave two vdd names separately for cmos and domino(only instances given separate, vdd value same only) with global ground for everything and no circuit change except this, but then I simulated power, the static power of cmos was more or less same, but static power of domino for 11 combination was going to uW range.

same circuit simulated with two different analysis on same condition gave 2 different results. How and why?

i am simulating static power on the flat regions of transient analysis fir input combo 00,01,10,11 for a temperature sweep from -270C to 30C with step 10 deg C.

Requesting help on this.

Genus synthesis | SystemVerilog in-code attribute assignment

SA202508198026 — Wed, 20 Aug 2025 10:43:31 GMT

Hi,

I’m trying to determine whether Cadence Genus supports SystemVerilog in-code synthesis attributes (similar to how Vivado does), for example:
(* dont_touch = "true" *) logic mysignal;
My goal is to simplify my timing.sdc file.

When I try this, Genus reports:
Warning : Unused attribute [VLOGPT-506]

I’ve tested several variations without success and haven’t found much documentation or examples for Genus specifically.
- Does Genus actually support this style of attribute assignment?
- If so, what is the correct syntax?
- Can it be applied to module instances, ports, registers, or nets?

Any insights would be greatly appreciated.

Thanks in advance,
Siebe

RE: Genus synthesis | SystemVerilog in-code attribute assignment

MK20251020799 — Mon, 20 Oct 2025 14:24:28 GMT

Unfortunately I was told by Cadence that this syntax is not currently supported (Case for reference: 46919575)

Ring oscillator separation gate delay and interconnect delay

SL202509028216 — Tue, 02 Sep 2025 15:06:45 GMT

Hello.

I have been reviewing the conventional methodologies for separating intrinsic gate delay and interconnect delay in ring oscillators,

such as

(1) varying the fan-out of the inverter

(2) modifying the interconnect length/width or shape

(3) changing the number of stages in the inverter chain.

However, I believe these approaches cannot rigorously decouple the two delays. This is because the overall circuit delay fundamentally results from the product of the total resistance and capacitance distributed across the entire circuit. Unless every cell is explicitly modeled as a network of R and C components and the contributions are separated at that level, the extracted delay will always contain coupled effects of both gate and interconnect. Do you think there is a feasible circuit modification or an alternative methodology that could more clearly separate gate delay and interconnect delay, beyond the conventional fan-out, interconnect geometry, or stage-count variations?

I would greatly appreciate your insights or suggestions on possible approaches. thankyou!

Reuse circuits

HSID — Wed, 06 Aug 2025 13:23:08 GMT

My company is researching a way to utilize reuse circuits. I know how to create them and bring them into a new design. What I am looking for is how do other companies handle the reuse circuits.

We would like to store them within EDM. I have not found any documents to really describe this. If someone is already using EDM to store reuse circuits and what their process is I would like to hear how you handle this.

Thanks

HSID

Logic Gates Circuit -to- VHDL -to- IC ??

HA202505189520 — Sun, 18 May 2025 21:48:50 GMT

Hi everyone i hope you are all doing well
im a schematic Entry designer. i design, create and draw logic gates/Flip Flops circuits using NI Multism PLD desinger, and then export that design into a VHDL file and synthesize in a FPGA IDE for real FPGA simulation.

- This an example of a digital button de-bouncer

Now i after i confirmed that circuit is working i want to create an actual IC out of it (or ASIC) but before manufacturing and chosign the fabricator, i have to create the transistor-level layout or photo mask (i actually don't know what that file called) and i heard that Cadence can do that but :
- Does Cadence support pure digital logic design, and which version of Cadence do i need?
- Do i have to start from scratch (rebuild it all manually) or just convert my VHDL file into that "transistor-level layout design"
any suggestions or information will be appreciated

Thank you for your time

Clock as Data Constraints

correllj — Tue, 13 May 2025 15:22:20 GMT

Hi,

I have several logic constructs where one clock samples another clock, such as phase detector, where the D pin of the flop is a clock.

When running "report_timing -lint", genus is reporting "Sequential data pins driven by a clock signal".

How do I set up the constraints to handle this?

Thanks!

signal (done) transition missing in (xcelium -simvision) during simulation but it is visible in xlinx vivado

RK202504233943 — Sat, 03 May 2025 08:08:58 GMT

Hello,

I'm running a behavioral simulation of my Verilog design using both Xilinx Vivado and Cadence Xcelium/SimVision.

In Vivado, I can clearly see a signal (indicating end-of-count/status) rising at a specific simulation time (~120,598 ns), as expected. However, in Xcelium/SimVision, that signal stays low throughout the simulation, even though the rest of the signals (e.g., clock, reset, counter) behave the same in both tools.

same code runs on both machine but i can see clearly see transition of signal "done" in vivado tool but this signal cant be seen in simvision throughout the simualtion. when i try to set time as 145000 around in signal and try to move cursor forward arrow cursor it shows with red warning " to advance simulation to next edge of selected signal,you must enable the watching live data from simulator" .to address this i rightclik on selected signal and choose watch but nothing works.

in my testbench code i am terminating simulation at 145000ns ($finish) but with this timing window there is no any transition of my slected ignal (done) in simvision but with same timing delay (145000ns ($finish)) on xilinx vivado it shows very clear transition.

regrading abnormal working of xcelium simulator during wavefrom simulation

RK202504233943 — Thu, 24 Apr 2025 06:34:41 GMT

hellow cadence support team,

i am facing an issue in xcelium simulator while simulating verilog code. when i try to run signal wavefrom it does nto working. it comes with pop op windows which says "" Recovery: Xcelium simulator Terminated Abnormally""

[ XM-SIM terminated unexpectedly] this happen when ever i click on run button then it shows pop op window with terminated simulation message.

my linux version is : 8.9 (red hat)

xcelium version : 22.03-s012

it would be great help if you can address this issue and kindly resolves this problem.

i need very fast so please please if you can provide please !!!

Using ChipWare (CW) Components in Quartus FPGA Builds?

SL202501311657 — Fri, 31 Jan 2025 15:09:19 GMT

Is there a way to use encrypted ChipWare (CW) components in a Quartus FPGA build flow?

which tools support Linting for early stages of Digital Design flow?

TR20240805746 — Thu, 03 Oct 2024 19:08:53 GMT

I am trying to understand the Linting process. I know that mainly JasperGold is the tool for this purpose. Though I think JasperGold is more suited for later stages of the design. As a RTL Design Engineer, I want to make sure that if another tool has the capability of doing Linting earlier in the flow. for example, does Xcelium, Genus or Confomal support linting. I have seen some contradicting information online regarding this topic, though I can't find anything related to Linting on any of these tools.

Thanks

RE: which tools support Linting for early stages of Digital Design flow?

ckomar — Mon, 02 Dec 2024 20:07:30 GMT

In general, I think any tool that parses RTL has some linting capability but I cannot comment on the extent of Conformal's capabilities. I can only say that Jasper is Cadence's comprehensive linting solution.

RE: which tools support Linting for early stages of Digital Design flow?

TR20240805746 — Mon, 02 Dec 2024 18:23:40 GMT

Thank you very much Ckomar. So we can say that Conformal doesn't have any Linting features. Right?

RE: which tools support Linting for early stages of Digital Design flow?

ckomar — Mon, 02 Dec 2024 14:27:02 GMT

JasperGold Superlint is absolutely geared for comprehensive early (or late) RTL linting. Its complementary auto formal checks can further help the designer uncover common issues not found by structural lint. Please reach out to me using my userid at cadence.com if you want to discuss further.

RE: Asking for a software suggestion.

Jesswade — Mon, 02 Dec 2024 12:48:05 GMT

To get started, you'll need to import your logic design into Cadence and then define the input parameters (like the different data you've exported from other software). Next, you can use tools like Cadence's Design Compiler or Innovus to synthesize the design and analyze the delay, power dissipation, and area for different input conditions. You might also want to set up a design corner (variety of conditions) to evaluate the maximum, minimum, and average results. Don’t hesitate to check Cadence’s documentation for specific steps or reach out to a community forum for tips along the way!

Asking for a software suggestion.

SJ202410152653 — Tue, 15 Oct 2024 23:05:41 GMT

Hi. I'm a very new learner on Cadence. I want to synthesis my logic design for the maximum, minimum and an average results of delay, power dissipation and area under varying multiple inputs of different data. The different data will be exported from other software results. I'm lost on the steps/processes I should do.

Could anyone suggest me on which software and/or function or scripts I should use to achieve these results?

RE: which tools support Linting for early stages of Digital Design flow?

Jesswade — Tue, 26 Nov 2024 09:15:07 GMT

For early-stage RTL linting, use SpyGlass (Synopsys) or Ascent Lint (Real Intent). These are dedicated tools for linting. Xcelium, Genus, and Conformal are not designed for comprehensive linting, though they may catch some basic issues during simulation or synthesis. Let me know if you need detailed setup guidance!

ask some functions that we don't know if it exists

RONZYRR — Wed, 25 Sep 2024 15:41:09 GMT

We have a big circuit having 12K gates totally and trying to show it in one page slide visually. But it is so hard for us to shrink it down from gate-level to module-level. Do you have any function like these:

Toggle wires on and off
“Right click” elements and group them into black boxes
Quickly left or right align elements to clean up pictures

Unmapped points

GN20240831236 — Mon, 23 Sep 2024 06:07:07 GMT

Hi ,

I am using conformal v23.2 for LEC checking b/w netlist vs Netlist. I am getting 8 not mapped points(z) in revised but when i check in mapping manager it showing 0 Not mapped points and showing this 8 not mapped points in extra unmapped section z(f) snps_scan_out_6 .How to resolve this issue Pls help

regards,

Want to use Transmission Gate in my design?

Rohit B — Fri, 21 Jun 2024 16:19:26 GMT

I want to use a transmission gate in my design, but it is not available as a standard cell for Genus RTL synthesis. How can I perform an analysis of area, power, and critical path delay that includes the transmission gate alongside standard cells?

Could you provide guidance or a methodology for integrating custom cells, like the transmission gate, into the synthesis flow for accurate analysis?

removing cdn_loop_breakers from netlist

Ganga Vinod — Wed, 12 Jun 2024 04:49:49 GMT

I was trying to remove the cdn_loop_breaker cells from the netlist.
When I tried the below 2 things, it removing the cdn_loop_breaker cells but while connecting the cdn_loop_breaker cell input to its proper connection, its somehow misleading the connections

Things i tried:
1. remove_cdn_loop_breaker -instances *cdn_loop_breaker*
then i just ran remove_cdn_loop_breaker comand without the -instances switch
2. remove_cdn_loop_breaker

both of the above things are not providing the proper connections after removing the loop_breaker_cells

Conformal CEC checking

Sameerpy — Tue, 19 Mar 2024 21:04:55 GMT

Below is showing my Master.v

********************************************************************************************************************************************************************************************************************

///////ALU
module ALU (
    input [31:0] A,B,
    input[3:0] alu_control,
    output reg [31:0] alu_result,
    output reg zero_flag
);
    always @(*)
    begin
        // Operating based on control input
        case(alu_control)

        4'b0001: alu_result = A+B;
        4'b0010: alu_result = A-B;
        4'b0011: alu_result = A*B;
        4'b0100: alu_result = A|B;
        4'b0101: alu_result = A&B;
        4'b0110: alu_result = A^B;
        4'b0111: alu_result = ~B;
        4'b1000: alu_result = A<<B;
        4'b1001: alu_result = A>>B;
        4'b1010: begin
            if(A<B)
            alu_result = 1;
            else
            alu_result = 0;
        end
        default: alu_result = A+B;

        endcase

        // Setting Zero_flag if ALU_result is zero
        if (alu_result)
            zero_flag = 1'b1;
        else
            zero_flag = 1'b0;
    end
endmodule

/////CONTROL UNIT
/*
Control unit controls takes opcode, funct7, funct3 of the instruction code to determine
and control regwrite in IFU, alu control in ALU to execute proper instruction
*/
/*
Control unit controls takes opcode, funct7, funct3 of the instruction code to determine
and control regwrite in IFU, alu control in ALU to execute proper instruction
*/
module CONTROL(
    input [4:0] opcode,
    output reg [3:0] alu_control,
    output reg regwrite_control,memread_control,memwrite_control
);
    always @(opcode)
    begin
       case(opcode)
        5'b00001: begin alu_control=4'b0001; //add
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        5'b00010: begin alu_control=4'b0010; ///sub
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        5'b00011: begin alu_control=4'b0011; //mul
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b00100: begin alu_control=4'b0100; ///OR
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b00101: begin alu_control=4'b0101; ///AND
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        5'b00110: begin alu_control=4'b0110; ///XOR
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b00111: begin alu_control=4'b0111; ///NOT
        regwrite_control=0; memread_control=0; memwrite_control=1;
        end
        5'b01000: begin alu_control=4'b1000; //SL
        regwrite_control=1; memread_control=1; memwrite_control=0;
        end
        5'b11001: begin alu_control=4'b1001; //SR
        regwrite_control=1; memread_control=1; memwrite_control=0;
        end
        5'b01010: begin alu_control=4'b1010; //COMPARE
        regwrite_control=1; memread_control=1; memwrite_control=0;
        end
        //5'b11010: begin ALU_control=4'b0000; //SW
        //regwrite_control=1; memread_control=0; memwrite_control=0;
        //end
        //5'b01010: begin ALU_control=4'bxxxx; //LW
        //regwrite_control=0; memread_control=0; memwrite_control=1;
        //end
        default : begin alu_control = 4'b0001;
        regwrite_control=1; memread_control=0; memwrite_control=0;
        end
        endcase
    end
endmodule

//////DATA MEMORY
module Data_Mem(
input clock, rd_mem_enable, wr_mem_enable,
input [11:0] address,
input [31:0] datawrite_to_mem,
output reg [31:0] dataread_from_mem );

reg [31:0] Data_Memory[8:0];

initial begin
   Data_Memory[0] = 32'hFFFFFFFF;
   Data_Memory[1] = 32'h00000001;
   Data_Memory[2] = 32'h00000005;
   Data_Memory[3] = 32'h00000003;
   Data_Memory[4] = 32'h00000004;
   Data_Memory[5] = 32'h00000000;
   Data_Memory[6] = 32'hFFFFFFFF;
   Data_Memory[7] = 32'h00000000;
   //Data_Memory[8] = 32'h00000008;
   //Data_Memory[9] = 32'h00000009;
   //Data_Memory[10] = 32'h0000000A;
   //Data_Memory[11] = 32'h0000000B;
   //Data_Memory[12] = 32'h0000000C;
   //Data_Memory[13] = 32'h0000000D;
   //Data_Memory[14] = 32'h0000000E;
   //Data_Memory[15] = 32'h0000000F;
   //Data_Memory[16] = 32'h00000010;
   //Data_Memory[17] = 32'h00000011;
   //Data_Memory[18] = 32'h00000012;
   //Data_Memory[19] = 32'h00000013;
   //Data_Memory[20] = 32'h00000014;
   //Data_Memory[21] = 32'h00000015;
   //Data_Memory[22] = 32'h00000016;
   //Data_Memory[23] = 32'h00000017;
   //Data_Memory[24] = 32'h00000018;
   //Data_Memory[25] = 32'h00000019;
   //Data_Memory[26] = 32'h0000001A;
   //Data_Memory[27] = 32'h0000001B;
   //Data_Memory[28] = 32'h0000001C;
   //Data_Memory[29] = 32'h0000001D;
   //Data_Memory[30] = 32'h0000001E;
   Data_Memory[31] = 32'h0000001F;

    end
    always@(posedge clock) begin
       if(wr_mem_enable) begin
           Data_Memory[address] <= datawrite_to_mem;
       end
       else if(rd_mem_enable) begin
              dataread_from_mem <= Data_Memory[address];
       end
       else begin
              dataread_from_mem <= 32'h00000000;
       end
    end
endmodule

/////INST MEM
/*

*/
module INST_MEM(
    input [31:0] PC,
    input reset,
    output [31:0] Instruction_Code
);
    reg [7:0] Memory [43:0]; // Byte addressable memory with 32 locations


    assign Instruction_Code = {Memory[PC+3],Memory[PC+2],Memory[PC+1],Memory[PC]};



    initial begin
            // Setting 32-bit instruction: add t1, s0,s1 => 0x00940333
            Memory[3] = 8'b0000_0000;
            Memory[2] = 8'b0000_0001;
            Memory[1] = 8'b0111_1100;
            Memory[0] = 8'b0000_0001;
            // Setting 32-bit instruction: sub t2, s2, s3 => 0x413903b3
            Memory[7] = 8'b0000_0000;
            Memory[6] = 8'b0000_0110;
            Memory[5] = 8'b1000_1111;
            Memory[4] = 8'b1110_0010;
            // Setting 32-bit instruction: mul t0, s4, s5 => 0x035a02b3
            Memory[11] = 8'b0000_0000;
            Memory[10] = 8'b0000_0101;
            Memory[9] = 8'b0111_1100;
            Memory[8] = 8'b0000_0011;
            // Setting 32-bit instruction: or t3, s6, s7 => 0x017b4e33
            Memory[15] = 8'b1111_1111;
            Memory[14] = 8'b1111_0100;
            Memory[13] = 8'b1010_0000;
            Memory[12] = 8'b1010_0100;
            // Setting 32-bit instruction: and
            Memory[19] = 8'b0000_0000;
            Memory[18] = 8'b0010_1001;
            Memory[17] = 8'b0001_1101;
            Memory[16] = 8'b0010_0101;
            // Setting 32-bit instruction: xor
            Memory[23] = 8'b0000_0000;
            Memory[22] = 8'b0001_1000;
            Memory[21] = 8'b0000_1101;
            Memory[20] = 8'b0110_0110;
            // Setting 32-bit instruction: not
            Memory[27] = 8'b0000_0000;
            Memory[26] = 8'b0010_1001;
            Memory[25] = 8'b0011_1101;
            Memory[24] = 8'b1100_0111;
            // Setting 32-bit instruction: shift left
            Memory[31] = 8'b0000_0000;
            Memory[30] = 8'b0101_0111;
            Memory[29] = 8'b1100_0110;
            Memory[28] = 8'b0000_1000;
            // Setting 32-bit instruction: shift right
            Memory[35] = 8'b0000_0000;
            Memory[34] = 8'b0110_1010;
            Memory[33] = 8'b1101_0010;
            Memory[32] = 8'b0111_1001;
            /// Setting 32-bit instruction: Campare
            Memory[39] = 8'b0000_0000;
            Memory[38] = 8'b0111_1010;
            Memory[37] = 8'b1101_0010;
            Memory[36] = 8'b0110_1010;
            /// Setting 32-bit instruction:
            Memory[43] = 8'b0000_0000;
            Memory[42] = 8'b0111_0111;
            Memory[41] = 8'b1101_0010;
            Memory[40] = 8'b0111_0010;
        end

endmodule

//IFU
/*
The instruction fetch unit has clock and reset pins as input and 32-bit instruction code as output.
Internally the block has Instruction Memory, Program Counter(P.C) and an adder to increment counter by 4,
on every positive clock edge.
*/
module IFU(
    input clock,reset,
    output [31:0] Instruction_Code
);
reg [31:0] PC = 32'b0; // 32-bit program counter is initialized to zero


    always @(posedge clock, posedge reset)
    begin
        if(reset == 1) //If reset is one, clear the program counter
        PC <= 0;
        else
        PC <= PC+4;   // Increment program counter on positive clock edge
    end
    // Initializing the instruction memory block
    INST_MEM instr_mem(.PC(PC),.reset(reset),.Instruction_Code(Instruction_Code));

endmodule

///MUX

module Mux_2X1 (
    input mem_rd_select, // rd_mem_enable
    input wire [31:0] dataread_from_mem, regdata2,

    output reg [31:0] mux_out
);

always @(mem_rd_select or dataread_from_mem or regdata2) begin
    if (mem_rd_select == 1)
        mux_out <= dataread_from_mem ;
    else
        mux_out <= regdata2;
    end
endmodule

//DFlipFlop
module DFlipFlop(D,clock,Q);
input D; // Data input
input clock; // clock input
output reg Q; // output Q
always @(posedge clock)
begin
Q <= D;
end
endmodule

///DATA path

module DATAPATH(
    input [4:0]Read_reg_add1,
    input [4:0]Read_reg_add2,
    input [4:0]Reg_write_add,
    input [3:0]Alu_control,
    input [11:0]Address,
    input Wr_reg_enable,Wr_mem_enable,Rd_mem_enable,
    input clock,
    input reset,
    output OUTPUT
    );

    // Declaring internal wires that carry data
    wire zero_flag;
    wire [31:0]Dataread_from_mem;
    wire [31:0]read_data1;
    wire [31:0]read_data2;
    wire [31:0]Mux_out;
    wire [31:0]Alu_result;
    //wire [31:0]datawrite_to_reg;

    // Instantiating the register file
    REG_FILE reg_file_module(.reg_read_add1(Read_reg_add1),.reg_read_add2(Read_reg_add2),.reg_write_add(Reg_write_add),.datawrite_to_reg(Alu_result),.read_data1(read_data1),.read_data2(read_data2),.wr_reg_enable(Wr_reg_enable),.clock(clock),.reset(reset));

    // Instanting ALU
    ALU alu_module(.A(read_data1), .B(Mux_out), .alu_control(Alu_control), .alu_result(Alu_result), .zero_flag(zero_flag));

    //Mux
    Mux_2X1 mux(.mem_rd_select(Rd_mem_enable),.dataread_from_mem(Dataread_from_mem),.regdata2(read_data2),.mux_out(Mux_out));

    //Data Memory
    Data_Mem DM(.clock(clock),.rd_mem_enable(Rd_mem_enable),.wr_mem_enable(Wr_mem_enable),.address(Address),.datawrite_to_mem(Alu_result),.dataread_from_mem(Dataread_from_mem));

    // Dflipflop
    DFlipFlop DF (.D(zero_flag), .Q(OUTPUT),.clock(clock));
endmodule

/*
A register file can read two registers and write in to one register.
The RISC V register file contains total of 32 registers each of size 32-bit.
Hence 5-bits are used to specify the register numbers that are to be read or written.
*/

/*
Register Read: Register file always outputs the contents of the register corresponding to read register numbers specified.
Reading a register is not dependent on any other signals.

Register Write: Register writes are controlled by a control signal RegWrite.
Additionally the register file has a clock signal.
The write should happen if RegWrite signal is made 1 and if there is positive edge of clock.
*/
module REG_FILE(
    input [4:0] reg_read_add1,
    input [4:0] reg_read_add2,
    input [4:0] reg_write_add,
    input [31:0] datawrite_to_reg,
    output [31:0] read_data1,
    output [31:0] read_data2,
    input wr_reg_enable,
    input clock,
    input reset
);

    reg [31:0] reg_memory [31:0]; // 32 memory locations each 32 bits wide

    initial begin
        reg_memory[0] = 32'h00000000;
        reg_memory[1] = 32'hFFFFFFFF;
        reg_memory[2] = 32'h00000002;
        reg_memory[3] = 32'hFFFFFFFF;
        reg_memory[4] = 32'h00000004;
        reg_memory[5] = 32'h01010101;
        reg_memory[6] = 32'h00000006;
        reg_memory[7] = 32'h00000000;
        reg_memory[8] = 32'h10101010;
        reg_memory[9] = 32'h00000009;
        reg_memory[10] = 32'h0000000A;
        reg_memory[11] = 32'h0000000B;
        reg_memory[12] = 32'h0000000C;
        reg_memory[13] = 32'h0000000D;
        reg_memory[14] = 32'h0000000E;
        reg_memory[15] = 32'h0000000F;
        reg_memory[16] = 32'h00000010;
        reg_memory[17] = 32'h00000011;
        reg_memory[18] = 32'h00000012;
        reg_memory[19] = 32'h00000013;
        reg_memory[20] = 32'h00000014;
        reg_memory[21] = 32'h00000015;
        //reg_memory[22] = 32'h00000016;
        //reg_memory[23] = 32'h00000017;
        //reg_memory[24] = 32'h00000018;
        //reg_memory[25] = 32'h00000019;
        //reg_memory[26] = 32'h0000001A;
        //reg_memory[27] = 32'h0000001B;
        //reg_memory[28] = 32'h0000001C;
        //reg_memory[29] = 32'h0000001D;
        //reg_memory[30] = 32'h0000001E;
        reg_memory[31] = 32'hFFFFFFFF;
    end

    // The register file will always output the vaules corresponding to read register numbers
    // It is independent of any other signal
    assign read_data1 = reg_memory[reg_read_add1];
    assign read_data2 = reg_memory[reg_read_add2];

    // If clock edge is positive and regwrite is 1, we write data to specified register
    always @(posedge clock)
    begin
        if (wr_reg_enable) begin
            reg_memory[reg_write_add] = datawrite_to_reg;
        end
   else
        reg_memory[reg_write_add] = 32'h00000000;
    end
endmodule

/////PROCESSOR

module PROCESSOR(
    input clock,
    input reset,
    output Output
);

    wire [31:0] instruction_Code;
    wire [3:0] ALu_control;
    wire WR_reg_enable;
    wire WR_mem_enable;
    wire RD_mem_enable;

    IFU IFU_module(.clock(clock), .reset(reset), .Instruction_Code(instruction_Code));

    CONTROL control_module(.opcode(instruction_Code[4:0]),.alu_control(ALu_control),.regwrite_control(WR_reg_enable),.memread_control(RD_mem_enable),.memwrite_control(WR_mem_enable));

    DATAPATH datapath_module(.Wr_mem_enable(WR_mem_enable),.Rd_mem_enable(RD_mem_enable),.Read_reg_add1(instruction_Code[9:5]),.Read_reg_add2(instruction_Code[14:10]),.Reg_write_add(instruction_Code[19:15]),.Address(instruction_Code[31:20]),.Alu_control(ALu_control),.Wr_reg_enable(WR_reg_enable), .clock(clock), .reset(reset), .OUTPUT(Output));

endmodule

**********************************************************************************************************************************************************

Below is my Synthesis.tcl file for genus synthesis

********************

set_attribute lib_search_path "/home/sameer23185/Desktop/VDF_PROJECT/lib"
set_attribute hdl_search_path "/home/sameer23185/Desktop/VDF_PROJECT"
set_attribute library "/home/sameer23185/Desktop/VDF_PROJECT/lib/90/fast.lib"
read_hdl Master.v
elaborate
read_sdc Min_area.sdc
set_attribute hdl_preserve_unused_register true
set_attribute delete_unloaded_seqs false
set_attribute optimize_constant_0_flops false
set_attribute optimize_constant_1_flops false
set_attribute optimize_constant_latches false
set_attribute optimize_constant_feedback_seqs false
#set_attribute prune_unsued_logic false
synthesize -to_mapped -effort medium
write_hdl > report/HDL_min_Netlist.v
write_sdc > report/constraints.sdc
write_script > report/synthesis.g
report_timing > report/synthesis_timing_report.rep
report_power > report/synthesis_power_report.rep
report_gates > report/synthesis_cell_report.rep
report_area > report/synthesis_area_report.rep
gui_show

**********************************************

WHEN I COMPARING MY GOLDEN.V WITH HDL_min_Netlist.v during conformal , I got these non-equivalent point for every reg memory and for every data memory. I don't know what to do with these non-equivalent point. I've been stuck here for the past four days. Please help me in this and how can I remove this non- equivalent point , since I am new to this I really don't know what to do.

RE: Conformal CEC checking

Fotios Nt — Tue, 30 Apr 2024 09:05:46 GMT

Hi,
There's a whole lot of issues that need fixing in your flow. You are for one using a very old synthesis approach that's not maintained for almost 10 years now (the synth -to_mapped command). Instead, if you just want a new-ish but very barebones synthesis script load up genus and run write_template command, and then fill in the blanks (libraries sdc etc). Flowtool is a much better approach, but it has a steeper learning curve

Then, you need to run LEC in 2 steps:
1) RTL to fv_map (fv_map is an intermediate netlist generated from syn_map, which is the upgraded version of synthesize -to_mapped) . This LEC dofile will get automatically generated for your when you run syn_map, and by default will be found in fv/<top level name>/rtl_to_fv_map.do
2) fv_map to your final synthesis netlist. Use write_do_lec -golden fv_map (this is a reserved keyword, use it as is) -revised <your revised netlist here> to generate that dofile

Conformal non-equivalences cannot be debugged via a simple screenshot unfortunately. You need to go to the mapping manager, open the diagnosis manager, and look at the GUI for clues. There is a conformal RAK as well that contains a lab that should get you familiar with that flow