Mixed-Signal Design - Recent Threads

NPORT and MTLINE S Parameter File

PN202601231518 — Thu, 16 Jul 2026 15:55:33 GMT

Both of these can take an S parameter file (touchstone).

But MTLINE requires a line length and NPORT does not....why ?

AMS: how to probe signals in ADE from a schematic instantiated within a system verilog module

MC20250412421 — Sun, 21 Jun 2026 20:21:04 GMT

Hello everyone !

I have the following hierarchy for my testbench (from highest to lowest level):

1) a schematic view for my testbench which instantiates a systemverilog instance named DUT

2) inside DUT, I have instantiated a schematic cellview with the following systemverilog syntax:

myModule my_module_inst0 (
.input_A (signal_A)
);

3) inside my_module_inst0 I have a simple schematic with a few analog signals and dc/tran sources, for example there is a net named my_net.

Now my question is: how do I probe my_net inside ADE ?
With any standard schematic hierarchy I would simply click on "Add new output" and then write "/DUT/my_module_inst0/my_net" to probe the voltage signal of that net however I tried that and it simply does not find that net.

My simulation does work and does output correct signals at the toplevel so I know the connect modules work. Also, I had to add args -ams_ucm and -sv_ms to my test to the additional arguments in the AMS options for the simulation to work.
I also checked in the config view that the hierarchy was indeed correct so that should be fine.
I am using version IC23.1-64b.ISR8.40 of virtuoso and xrun 23.03-s011.

Seems like it should be quite a basic question unfortunately I did not find the answer in the documentation or the forums so I would be very grateful if anyone could help me out with that.

Thanks in advance and have a great day !

Mike

Bad AMS simulation Accuracy for L2E Conversion

Khalid Eissa — Fri, 08 May 2026 11:03:13 GMT

Hello,

I am trying to simulate a PLL circuit where the input clock is coming from a Verilog model (logic) but the phase detector is schematic. So I need to convert this logic signal to electric

The issue is that after L2E conversion I get the electric clock with a delay compared to the logic clock and that delay seem to be random each cycle (subject to simulation step) This adds a lot of phase error to the PLL input and finds its way to the output of the PLL.

I want cadence to somehow always get the electric clock to be as close as possible to the logic clock, something like within 10fs of it or at least have a fixed delay that is not changing with each cycle

I am using Spectre-X CX (highest accuracy) and I tried different connect-rules like rise/fall times to be as low as 10fs but does not seem to fix the issue. I tried APS as well but does not improve results

Any ideas how to fix this?

AMS/SimVision simulation

PE202503078250 — Tue, 21 Apr 2026 15:13:04 GMT

I simulated a verilog testbench with a module consisting of a synthesized gate level netlist in SimVision. It seems to be working (at least giving an output signal that looks valid)

However when I ran the same simulation in Cadence Virtuoso using the AMS simulator, the output seems to be in the High-Z/undefined state. Is there any simulation setting that I'm missing ? The testbench in Virtuoso doesnt have any analog blocks. All are verilog modules. So then I assume any setting mistakes related to the ConnectModules can be ruled out. However, the RTL code (of the corresponding gate level netlist) indeed works in Virtuoso.

simvision analog variables and signals display issue

mxgong — Wed, 25 Mar 2026 23:59:57 GMT

Hi,

I am running ams simulation in the interactive mode.

However, the simulation has gone through, but I can only observe the digital signals. All analog signals (including inputs and outputs) and variables within the analog begin block are showing no value in the waveform window.

Here vin[8] is a net in the testbench schematic. triggers_out[x] are digital signals. Ceq is a real number inside the analog begin block.

When I stop the simulation and open result browser, the signals in schematics are saved there.

Thanks

Minxiang

Cadence Hierarchy Editor

PE202503078250 — Wed, 25 Mar 2026 13:53:56 GMT

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/33268/hierarchy-editor---how-to-use-library-list

I understood from the above old discussion that "when you instantiate a module in a Verilog module, you only reference the cell and not the library - the library is "loose". The library list is used to resolve the library in those cases. Consequently, it should only affect instances inside Verilog views (or similar) where the library needs to be identified."

I have a config view created in say LibA. My corresponding Test Bench has a top level verilog module (which belongs to LibB) that instantiates multiple verilog modules which are present in both LibA and LibB. I want the HED to have the instantiated modules to point to the modules in LibB. However it doesnt happen and despite giving only LibB in the Library list it still points to LibA. Is there way to do that ? Is there a way to specify the library where each verilog module has to point to ? say for instance module1 from LibA, module2 from LibB etc....

Calling AMS control file in ADE AMS Simulations

Cherrihane — Mon, 16 Feb 2026 22:44:30 GMT

I created an ams control file amscf.scs and added an amsd block within it. I want to use this file in my AMS simulations, how can i included it in ADE?

Replacing cell in an analog on top testbench by an external HDL module that has different name

Cherrihane — Mon, 16 Feb 2026 22:41:31 GMT

I have an analog-on-top testbench and would like to replace a specific cell with a digital module. The digital module and its submodules are defined in external files without existing cell views. I have included these files via Simulation > Options > AMS Simulator > Include Option Settings.

However, the top module name in the Verilog file differs from the name of the cell view I am replacing. How can I configure the mapping so the tool replaces this cell with the provided Verilog module file?

I am using AMS designer through ADE GUI (AVUM flow)

AMS Connect module

SH202507179147 — Thu, 12 Feb 2026 12:10:34 GMT

Im new to AMS-Verification.
I have modeled differential amplifier in VAMS.
Now I want to verify it using RNM. Have created a RNM-TB and connectmodule too, for electrical to real and real to electrical.
but im getting error in connectmodule.

What should be included in connectmodule:
input, output, electrical: must
real, wreal?

`include "disciplines.vams"

//real to electrical; for stimulus conversion
connectmodule real_to_ele ( vin_r, vin_e);
input vin_r;
output vin_e;
real vin_r;
electrical vin_e;
analog begin
V(vin_e) <+ vin_r ;
end
endmodule

//electrical to real; for observing the output
connectmodule elec_to_real( vout_e, vout_r);
input vout_e;
output vout_r;
electrical vout_e;
real vout_r;
analog begin
vout_r = V(vout_e);
end
endmodule

script to capture the waveforms to an image in SIMVISION

PedroC — Mon, 09 Feb 2026 15:44:03 GMT

Hi,

I am doing a script that should capture the waveforms, in simvision waveform viewer, for documentation.

The basic idea is, as the user develops the SV sequence there will be some function that will create markers.

Example

.......

setmarker("uvlo_thr_START");

....

setmarker("uvlo_thr_END");

....

These markers will be named with some meaningful text appended by the the keywords "START" and "END".

When there is a match, between the name in the markers, an image will be captured between the markers. You can imagine a simulation with many markers and tens of images being captured automatically to your disk to be used in a powerpoint or another type of document.

The first step is just to export the image using the funcionality provided by the command "print" from SimVision. However, when I save the image in any format (I am using PS/EPS), it will give the same space to the waveforms as to the left pane where the name of all signals are.

The first image shows the simvision screen capture with a snapshot tool. The second, the same image but with the simvision's print command.

As you can see, this is not what we want.

How can I solve this?

Kind regards,

Pedro

Specification for Digital Bus Value

Kevin T Buck — Mon, 26 Jan 2026 18:30:23 GMT

Is it possible in a mixed signal simulation to set a specification for a digital bus output? I'm taking the value of a digital output at a specified time period and the format is 0bxxxxxxx (i.e. it could be 0b0000001 or 0b0001101, etc.). I would like to set a numerical decimal comparison to the digital output but the output just evaluates to fail no matter what the digital output is. For now I'm converting it to a normalized output with awvDigital2Analog and comparing to that value but I couldn't find anything specifying if it's possible to compare directly to a bus value.

cadence connect rules not found in ams installation

RM202411052544 — Mon, 29 Dec 2025 20:29:44 GMT

Hello!

I was simulating a simple full adder(following a youtube video) using verilog, and after creating the symbol, the config view and everything, we came to the part where we need to do the interface element setup. But there was nothing there. It gave me the message "connect rules not found in ams installation". I am new to cadence and am on a very old system. I think the cadence version is 6.1.7, but I have no clue how to get any more details. Any help you be really appreciated!!

save AHDL variables

PE202503078250 — Wed, 03 Dec 2025 15:12:56 GMT

I'm using virtuoso version IC23.1-64b and using the ams simulator.

I'm using a Verilog block, and want to plot certain AHDL variables within the block.

However, I can plot it by saving all the nets and all AHDL variables in the save options, which does in fact increase the simulation time.

How can I plot only the selected AHDL variables and the selected nets ?

I came across the below post

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=anasimhelp.xml&title=Virtuoso%20ADE%20Environment%20Variables%20Reference%20--%20saveahdlvars%20-%20saveahdlvars&hash=&c_version=IC25.1&path=anasimhelp/anasimhelpIC25.1/saveahdlvars.html

But, is there a way to do it in the GUI (in the above mentioned Cadence version) ?

Unfamiliar and confused about analog-on-top design flow and tools

JD202506199142 — Mon, 17 Nov 2025 20:42:58 GMT

I am not sure what the best tools and flow is to create, synthesize, test, and layout, the digital part of my mixed signal design. So far I have seen that I can use Xcelium to test verilog and simulate it, Genus to synthesize verilog into gates and a netlist, and Innovus for placement and routing. I would like to know if this is the cleanest design flow I can follow or if there is a simpler combination of tools I can use to design and layout the digital logic for my mixed signal design. Additionally, if I did do the design this way and brought a netlist into virtuoso to test along side my analog circuitry, would the Spectre AMS Designer be the best tool for verification? I'm fairly new to these tools and mixed-signal design, despite lots of searching I'm still confused so I would appreciate help.

IC6.1.8: Introduction to AMS Designer Simulation ( 10 Oct 2025) - RAK : Issue of NMOS and PMOS transistor not in its range of parameters

CM202508086341 — Tue, 11 Nov 2025 16:29:31 GMT

I recently downloaded a RAK for AMS simulation, and I followed the instructions up to the netlisting phase, which was successful. However, during simulation, an error occurred indicating that the M0 (NMOS) and M1 (PMOS) transistors in the inverter had their length, width, or area values outside the specified range of lmax-lmin, among other issues.

Programmable voltage/current sources

LostBoy — Tue, 04 Nov 2025 21:37:46 GMT

I know that it is possible to control/program voltage and current sources in debug mode using the SimVision/Xcelium terminal or TCL scripts.

I would like to set something like this up for my analog simulations. Are there any step-by-step instructions for doing this?

Period jitter and TiE Jitter simulations of RC Relaxation Oscillator

GirishW — Thu, 23 Oct 2025 12:10:06 GMT

Hi There,

I am looking to measure TiE jitter & Period Jitter of 300KHz RC Relaxation oscillator. For it, I have setup Transient noise analysis simulation ( spectre transient noise analysis training).

I did able to plot DSB PN. But, I am unable to find option to plot /measure Period Jitter.

Can you please help me with it or point to relevant documentation.

Thank You !

rand_bit_stream not reproducible across runs despite setting seed

MB202509174350 — Wed, 15 Oct 2025 11:11:46 GMT

Hi all,

I am building an LVDS RX and so needed a block to supply random data. Virtuoso ADE has a built-in Verilog-A cell called rand_bit_stream.

Even though you can set a seed value, it seems to ignore it. Different simulation runs have a totally different waveform.

Is this a known problem, or am I doing something wrong?

I am using VIrtuoso IC23.1 and Spectre 23.1.0.477.isr8 64bit.

Including variables from a fil

AA202510057331 — Sun, 05 Oct 2025 19:19:13 GMT

Hi,

I am using

IC25.1,

Spectre 24.1.0.288.isr5

Xcelium 25.03

I am trying to include variables from an external file so that they are recognized and used in my simulation, along with the other variables defined in the Maestro view GUI.

If it were a fully continuous-time simulation using just one of Spectre engines (APS, X, ..., etc), I can easily do that by putting my variables in a file "my_vars.scs" and including them in my model libraries.

However, when I want to do something similar in an AMS environment (where a cds_globals.vams is auto-created and populated with variables from the maestro view), the variables in "my_vars.scs" are not recognized during the initial "netlisting" and thus cause an error.

How/Where can I include a file with those variables, so that they are recognized during netlisting?

Or is there a way to alter the way "cds_globals.vams" file is generated so that it could auto-include a file containing the variables -after the "cds_globals" module header- from the external file and pass them along with all other GUI-defined variables?

Things I tried:

I tried copying the generated "cds_globals.vams" file to be "cds_globals_mine.vams", and manually added an include statement to include "my_vars.vams" after the "cds_globals" module header. Then using an "hdl.var" file with

DEFINE XRUNOPTS /path_to_/cds_globals_mine.vams

It includes my variables but, the issue with that is that it doesn't update values if changes were made on the GUI anymore.

Simulation of VerilogA model of a VCO ?

PE202503078250 — Tue, 30 Sep 2025 15:05:55 GMT

I'm using a very simple verilogA model of a VCO and running HB as well as PSS simulations, but neither of them converge. However, the transient simulation runs.
Is there some simulation engine specific reason behind this or are there some specific settings to be used ?

max usage of CPU cores in spectre/aps++ simulation

Tarique mohd — Sat, 06 Sep 2025 11:40:09 GMT

we have machine of 48 CPU cores, In case of big size circuit simulation, the %CPU is being used only 100 but last time we have used upto 700. could you please suggest settings in simulation environment so i can use to maximum available resources and reduce simulation time,

could you suggest bets way to use optimally?

BR, Tarique

DC convergence problem with Basic ring amplifier

SC202503236954 — Wed, 03 Sep 2025 05:40:54 GMT

I made some basic ring amplifier with Virtuoso, but DC simulation didn't work well.

Below is the schemetic of Bacis Ring amplifier that I made with Virtuoso.

Can anyone tell me what I did wrong with schemetic or simulation?

Attach load to a pin for AMS verification

PedroC — Mon, 01 Sep 2025 10:05:54 GMT

Hi,

I would like to have a voltage/current source that I could attach to any pin (programatically maybe). For example, I may need to pull the output of an LDO to ground.

How can I have a source that I can refer to the pin I want it to be attached to in order to create an over-voltage or under-voltage?

Kind regards,

Pedro

White phase noise in VCO decays with frequency – not flat as expected

brunoalexandrefraga — Wed, 30 Jul 2025 21:30:50 GMT

Hi everyone,

I’m implementing a simple sinusoidal VCO in Verilog-A for phase noise analysis using PSS+PNOISE. I added white phase noise using only the white_noise function, as shown in the code snippet below. I expect the noise floor to remain flat (constant) at higher frequency offsets, but instead, it decays approximately at 20 dB/dec until it reaches the expected bottom value.

Verilog-A snippet:

`include "disciplines.vams"
`include "constants.vams"

module vco0 ( vctrl, out );

input vctrl; voltage vctrl;
output out; voltage out;
parameter real vmin=0;
parameter real vmax=vmin+1 from (vmin:inf);
parameter real fmin=1 from (0:inf);
parameter real fmax=2*fmin from (fmin:inf);

parameter real bottom = -130;
real wn_level = pow(10, bottom/10);

real freq, phase;
integer n;

real wn;

analog begin
 freq = (V(vctrl) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

 if (freq > fmax) freq = fmax;
 if (freq < fmin) freq = fmin;

 phase = 2*`M_PI*idtmod(freq, 0, 1, -0.5);

 wn = white_noise(wn_level, "vco_white");

 V(out) <+ sin(phase + wn);
end
endmodule

I’m attaching a plot from my PNOISE simulation where you can see this behavior. I’ve also included a reference line with a 20 dB/dec slope to highlight that the noise curve follows that same decline before reaching the bottom at -130 dBc/Hz. This seems to contradict the assumption that white phase noise should produce a flat region in the phase noise spectrum.

I also attached the configuration of my PSS and PNOISE simulation, as well as the testbench I'm using to this simulations.

Link for the files (images for configurations and responses): https://drive.google.com/drive/folders/1t1UDG6E_qu5o_2h0W1WK1M_lZ9LUtvHN?usp=sharing

Why is the white phase noise not flat as expected?

Any insights would be greatly appreciated. Thanks in advance!

Best regards,
Bruno.

Illegal argument for signal access function [4.3(AMSLRM)]. Verilog AMS error.

BS20240726490 — Mon, 07 Jul 2025 07:27:58 GMT

hello exports,

wonder if I can find some help here.

I want to display the analog signal's voltage at digital clock edge in VerilogAMS code. the compiler keeps telling me this hierarchical signal access is illegal. is there a way to achieve this? the hierarchy path is definitely right as it can compile if I remove "V()" although I don't get the right voltage answer.

ncelab: *E,ILLSARG (..../verilogams/verilog.vams,735|52): Illegal argument for signal access function [4.3(AMSLRM)].

module testbench

always @(negedge clk ) begin

...
$display("==== %g ", V(top.sub.leaf) );
...
end

analog begin

...

end

endmodule