Mixed-Signal Design - Recent Threads

Bad AMS simulation Accuracy for L2E Conversion

Khalid Eissa — Fri, 08 May 2026 11:03:13 GMT

Hello,

I am trying to simulate a PLL circuit where the input clock is coming from a Verilog model (logic) but the phase detector is schematic. So I need to convert this logic signal to electric

The issue is that after L2E conversion I get the electric clock with a delay compared to the logic clock and that delay seem to be random each cycle (subject to simulation step) This adds a lot of phase error to the PLL input and finds its way to the output of the PLL.

I want cadence to somehow always get the electric clock to be as close as possible to the logic clock, something like within 10fs of it or at least have a fixed delay that is not changing with each cycle

I am using Spectre-X CX (highest accuracy) and I tried different connect-rules like rise/fall times to be as low as 10fs but does not seem to fix the issue. I tried APS as well but does not improve results

Any ideas how to fix this?

RE: Bad AMS simulation Accuracy for L2E Conversion

Khalid Eissa — Fri, 08 May 2026 11:05:36 GMT

For doing L2E I tried the connect rules and also tried inserting a specific Verilog-AMS cell that does the L2E. I tried doing an intermediate conversion to wreal first then convert to voltage. Nothing seem to improve the accuracy at all

AMS/SimVision simulation

PE202503078250 — Tue, 21 Apr 2026 15:13:04 GMT

I simulated a verilog testbench with a module consisting of a synthesized gate level netlist in SimVision. It seems to be working (at least giving an output signal that looks valid)

However when I ran the same simulation in Cadence Virtuoso using the AMS simulator, the output seems to be in the High-Z/undefined state. Is there any simulation setting that I'm missing ? The testbench in Virtuoso doesnt have any analog blocks. All are verilog modules. So then I assume any setting mistakes related to the ConnectModules can be ruled out. However, the RTL code (of the corresponding gate level netlist) indeed works in Virtuoso.

simvision analog variables and signals display issue

mxgong — Wed, 25 Mar 2026 23:59:57 GMT

Hi,

I am running ams simulation in the interactive mode.

However, the simulation has gone through, but I can only observe the digital signals. All analog signals (including inputs and outputs) and variables within the analog begin block are showing no value in the waveform window.

Here vin[8] is a net in the testbench schematic. triggers_out[x] are digital signals. Ceq is a real number inside the analog begin block.

When I stop the simulation and open result browser, the signals in schematics are saved there.

Thanks

Minxiang

RE: simvision analog variables and signals display issue

Andrew Beckett — Fri, 03 Apr 2026 11:24:01 GMT

[quote userid="573754" url="~/cadence_technology_forums/f/mixed-signal-design/65873/simvision-analog-variables-and-signals-display-issue/1408175"]The previous one that worked with udb is using XCELIUM 64b 20.09-s009 and Spectre 64b 21.1.0.648.[/quote]

This worked before, then something broke, and as far as I know it's been fixed in the meantime. Hence my suggestion to use a later version (I'm just not sure whether it's on the XCELIUM or SPECTRE side - I would have to do some digging for that and I'm away from work for a few days...)

Andrew

RE: simvision analog variables and signals display issue

mxgong — Thu, 02 Apr 2026 17:22:15 GMT

The previous one that worked with udb is using XCELIUM 64b 20.09-s009 and Spectre 64b 21.1.0.648.

Minxiang

RE: simvision analog variables and signals display issue

Andrew Beckett — Thu, 02 Apr 2026 16:12:19 GMT

Can you try with a more recent version of both XCELIUM and Spectre? There were some UDB-related issues with waveform display (without knowing the precise details it's hard for me to check what broke when and was fixed when).

Andrew

RE: simvision analog variables and signals display issue

mxgong — Wed, 01 Apr 2026 18:40:28 GMT

If I change data format of spectre from udb to sst2. It works. I know simvision uses sst2 format, but I take a look in udb option that it did save the data in sst2. I have to manually reload database in simvision. Any root cause of this?

RE: simvision analog variables and signals display issue

mxgong — Thu, 26 Mar 2026 16:11:42 GMT

Hi Andrew,

Thanks for the quick reply.

the XCELIUM version is 23.03-a071 64b

the spectre version is 24.1.0.314.isr6 64b

Thanks

Minxiang

RE: simvision analog variables and signals display issue

Andrew Beckett — Thu, 26 Mar 2026 13:49:45 GMT

Minxiang,

Which XCELIUM and SPECTRE sub-versions are you using? (these will be reported in the simulation log)

Andrew

Cadence Hierarchy Editor

PE202503078250 — Wed, 25 Mar 2026 13:53:56 GMT

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/33268/hierarchy-editor---how-to-use-library-list

I understood from the above old discussion that "when you instantiate a module in a Verilog module, you only reference the cell and not the library - the library is "loose". The library list is used to resolve the library in those cases. Consequently, it should only affect instances inside Verilog views (or similar) where the library needs to be identified."

I have a config view created in say LibA. My corresponding Test Bench has a top level verilog module (which belongs to LibB) that instantiates multiple verilog modules which are present in both LibA and LibB. I want the HED to have the instantiated modules to point to the modules in LibB. However it doesnt happen and despite giving only LibB in the Library list it still points to LibA. Is there way to do that ? Is there a way to specify the library where each verilog module has to point to ? say for instance module1 from LibA, module2 from LibB etc....

Calling AMS control file in ADE AMS Simulations

Cherrihane — Mon, 16 Feb 2026 22:44:30 GMT

I created an ams control file amscf.scs and added an amsd block within it. I want to use this file in my AMS simulations, how can i included it in ADE?

RE: Calling AMS control file in ADE AMS Simulations

Saloni Chhabra — Tue, 17 Feb 2026 17:05:32 GMT

You can include it through Options -> AMS Simulator -> Include Option Settings -> Include Options (tab) -> Files on xrun command line

Saloni

RE: Replacing cell in an analog on top testbench by an external HDL module that has different name

Kevin T Buck — Tue, 17 Feb 2026 16:53:33 GMT

As far as I'm aware I don't think this is possible. You could generate a wrapper cell with the same name and instantiate your verilog block within the wrapper to work around this.

Replacing cell in an analog on top testbench by an external HDL module that has different name

Cherrihane — Mon, 16 Feb 2026 22:41:31 GMT

I have an analog-on-top testbench and would like to replace a specific cell with a digital module. The digital module and its submodules are defined in external files without existing cell views. I have included these files via Simulation > Options > AMS Simulator > Include Option Settings.

However, the top module name in the Verilog file differs from the name of the cell view I am replacing. How can I configure the mapping so the tool replaces this cell with the provided Verilog module file?

I am using AMS designer through ADE GUI (AVUM flow)

AMS Connect module

SH202507179147 — Thu, 12 Feb 2026 12:10:34 GMT

Im new to AMS-Verification.
I have modeled differential amplifier in VAMS.
Now I want to verify it using RNM. Have created a RNM-TB and connectmodule too, for electrical to real and real to electrical.
but im getting error in connectmodule.

What should be included in connectmodule:
input, output, electrical: must
real, wreal?

`include "disciplines.vams"

//real to electrical; for stimulus conversion
connectmodule real_to_ele ( vin_r, vin_e);
input vin_r;
output vin_e;
real vin_r;
electrical vin_e;
analog begin
V(vin_e) <+ vin_r ;
end
endmodule

//electrical to real; for observing the output
connectmodule elec_to_real( vout_e, vout_r);
input vout_e;
output vout_r;
electrical vout_e;
real vout_r;
analog begin
vout_r = V(vout_e);
end
endmodule

RE: AMS Connect module

SH202507179147 — Fri, 13 Feb 2026 05:59:35 GMT

Im not sure of R2E and E2R, but I have got L2E and E2L.
can we do custom model for R2E and E2R?

RE: AMS Connect module

tpylant — Thu, 12 Feb 2026 22:28:13 GMT

There are R2E and E2R connectmodules that ship with the Cadence install. Have you looked at using those?

Tim

RE: script to capture the waveforms to an image in SIMVISION

PedroC — Mon, 09 Feb 2026 16:12:04 GMT

There's absolutely no problem. I will reach out to them.

Thanks a lot Andrew.

Kind regards,

Pedro

script to capture the waveforms to an image in SIMVISION

PedroC — Mon, 09 Feb 2026 15:44:03 GMT

Hi,

I am doing a script that should capture the waveforms, in simvision waveform viewer, for documentation.

The basic idea is, as the user develops the SV sequence there will be some function that will create markers.

Example

.......

setmarker("uvlo_thr_START");

....

setmarker("uvlo_thr_END");

....

These markers will be named with some meaningful text appended by the the keywords "START" and "END".

When there is a match, between the name in the markers, an image will be captured between the markers. You can imagine a simulation with many markers and tens of images being captured automatically to your disk to be used in a powerpoint or another type of document.

The first step is just to export the image using the funcionality provided by the command "print" from SimVision. However, when I save the image in any format (I am using PS/EPS), it will give the same space to the waveforms as to the left pane where the name of all signals are.

The first image shows the simvision screen capture with a snapshot tool. The second, the same image but with the simvision's print command.

As you can see, this is not what we want.

How can I solve this?

Kind regards,

Pedro

RE: script to capture the waveforms to an image in SIMVISION

Andrew Beckett — Mon, 09 Feb 2026 16:05:12 GMT

Pedro,

I'm not sure how to do this (or even if it's possible). You might try asking on the Functional Verification forum where there will be more SimVision expertise (I can't move your post as there's a bug where posts cannot be moved if they have attachments/images), or better still might be to contact customer support (log into http://ask.cadence.com and then use the Case menu to submit a support case). I'd love to experiment and try to solve this myself but don't have the bandwidth in the next couple of weeks to try this, sorry.

Andrew

Specification for Digital Bus Value

Kevin T Buck — Mon, 26 Jan 2026 18:30:23 GMT

Is it possible in a mixed signal simulation to set a specification for a digital bus output? I'm taking the value of a digital output at a specified time period and the format is 0bxxxxxxx (i.e. it could be 0b0000001 or 0b0001101, etc.). I would like to set a numerical decimal comparison to the digital output but the output just evaluates to fail no matter what the digital output is. For now I'm converting it to a normalized output with awvDigital2Analog and comparing to that value but I couldn't find anything specifying if it's possible to compare directly to a bus value.

cadence connect rules not found in ams installation

RM202411052544 — Mon, 29 Dec 2025 20:29:44 GMT

Hello!

I was simulating a simple full adder(following a youtube video) using verilog, and after creating the symbol, the config view and everything, we came to the part where we need to do the interface element setup. But there was nothing there. It gave me the message "connect rules not found in ams installation". I am new to cadence and am on a very old system. I think the cadence version is 6.1.7, but I have no clue how to get any more details. Any help you be really appreciated!!

RE: cadence connect rules not found in ams installation

Andrew Beckett — Tue, 30 Dec 2025 21:06:07 GMT

There's this article: AMS Designer fails to find connect modules and errors out with "xmelab: *E,CUVNCM (./netlist.vams,27|21): No connection module found"

Also this post (it shows up for me in the "Related Topics" on the right side of this post in the forums): Error with AMS simulator "Connect rules are not found in your AMS installation"

Andrew

save AHDL variables

PE202503078250 — Wed, 03 Dec 2025 15:12:56 GMT

I'm using virtuoso version IC23.1-64b and using the ams simulator.

I'm using a Verilog block, and want to plot certain AHDL variables within the block.

However, I can plot it by saving all the nets and all AHDL variables in the save options, which does in fact increase the simulation time.

How can I plot only the selected AHDL variables and the selected nets ?

I came across the below post

https://support.cadence.com/apex/techpubDocViewerPage?xmlName=anasimhelp.xml&title=Virtuoso%20ADE%20Environment%20Variables%20Reference%20--%20saveahdlvars%20-%20saveahdlvars&hash=&c_version=IC25.1&path=anasimhelp/anasimhelpIC25.1/saveahdlvars.html

But, is there a way to do it in the GUI (in the above mentioned Cadence version) ?