Mixed-Signal Design - Recent Threads

RE: NPORT and MTLINE S Parameter File

PN202601231518 — Thu, 16 Jul 2026 16:52:02 GMT

Thanks...I always use MTLINE with length, my feeling has always been this is more accurate.
I see people using NPORT for transmission lines and your post has been a great clarification...thanks.

NPORT and MTLINE S Parameter File

PN202601231518 — Thu, 16 Jul 2026 15:55:33 GMT

Both of these can take an S parameter file (touchstone).

But MTLINE requires a line length and NPORT does not....why ?

RE: NPORT and MTLINE S Parameter File

Andrew Beckett — Thu, 16 Jul 2026 16:24:18 GMT

The nport component is designed to handle any kind of s-parameters, and has no knowledge of what they represent. From the frequency-domain s-parameter description, it has a couple of modelling approaches to build a time-domain approach (convolution-based when using linear or spline modes, or a rational fit when using bbspice mode). However, if the s-parameter file represents a long transmission line, it is hard to accurately model this (particularly the delay that would incur).

A better approach is to use the mtline component which is specifically designed to model transmission lines. In this case, the s-parameters are converted to equivalent per-length frequency-dependent RLGC parameters, but to do this it needs to know the physical length that the line represents (the RLGC input needs this too). The requirement for the length is purely because mtline knows that it's now representing a transmission line, and to accurately do the conversion it needs to know the length (which gets over the challenges that nport can have with long transmission lines).

Andrew

RE: AMS: how to probe signals in ADE from a schematic instantiated within a system verilog module

MC20250412421 — Thu, 25 Jun 2026 22:33:07 GMT

Anyone has an idea ? I didn't find anything in the docs about this.

AMS: how to probe signals in ADE from a schematic instantiated within a system verilog module

MC20250412421 — Sun, 21 Jun 2026 20:21:04 GMT

Hello everyone !

I have the following hierarchy for my testbench (from highest to lowest level):

1) a schematic view for my testbench which instantiates a systemverilog instance named DUT

2) inside DUT, I have instantiated a schematic cellview with the following systemverilog syntax:

myModule my_module_inst0 (
.input_A (signal_A)
);

3) inside my_module_inst0 I have a simple schematic with a few analog signals and dc/tran sources, for example there is a net named my_net.

Now my question is: how do I probe my_net inside ADE ?
With any standard schematic hierarchy I would simply click on "Add new output" and then write "/DUT/my_module_inst0/my_net" to probe the voltage signal of that net however I tried that and it simply does not find that net.

My simulation does work and does output correct signals at the toplevel so I know the connect modules work. Also, I had to add args -ams_ucm and -sv_ms to my test to the additional arguments in the AMS options for the simulation to work.
I also checked in the config view that the hierarchy was indeed correct so that should be fine.
I am using version IC23.1-64b.ISR8.40 of virtuoso and xrun 23.03-s011.

Seems like it should be quite a basic question unfortunately I did not find the answer in the documentation or the forums so I would be very grateful if anyone could help me out with that.

Thanks in advance and have a great day !

Mike

Cadence Hierarchy Editor

PE202503078250 — Wed, 25 Mar 2026 13:53:56 GMT

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/33268/hierarchy-editor---how-to-use-library-list

I understood from the above old discussion that "when you instantiate a module in a Verilog module, you only reference the cell and not the library - the library is "loose". The library list is used to resolve the library in those cases. Consequently, it should only affect instances inside Verilog views (or similar) where the library needs to be identified."

I have a config view created in say LibA. My corresponding Test Bench has a top level verilog module (which belongs to LibB) that instantiates multiple verilog modules which are present in both LibA and LibB. I want the HED to have the instantiated modules to point to the modules in LibB. However it doesnt happen and despite giving only LibB in the Library list it still points to LibA. Is there way to do that ? Is there a way to specify the library where each verilog module has to point to ? say for instance module1 from LibA, module2 from LibB etc....

RE: Cadence Hierarchy Editor

Andrew Beckett — Wed, 17 Jun 2026 13:35:47 GMT

Sorry, I missed the original post.

I don't know why it's failing to bind to the specific lib. You can even have an inherited lib list (this is not shown by default - you have to use the right mouse menu over the column headings) - as you've seen here I have:

if this is not working, I suggest you contact customer support so we can look at your data.

Andrew

RE: Cadence Hierarchy Editor

PE202503078250 — Tue, 16 Jun 2026 17:18:27 GMT

Has anyone got any idea on this ? I'm still not able to resolve this issue

RE: Bad AMS simulation Accuracy for L2E Conversion

Khalid Eissa — Fri, 08 May 2026 11:05:36 GMT

For doing L2E I tried the connect rules and also tried inserting a specific Verilog-AMS cell that does the L2E. I tried doing an intermediate conversion to wreal first then convert to voltage. Nothing seem to improve the accuracy at all

Bad AMS simulation Accuracy for L2E Conversion

Khalid Eissa — Fri, 08 May 2026 11:03:13 GMT

Hello,

I am trying to simulate a PLL circuit where the input clock is coming from a Verilog model (logic) but the phase detector is schematic. So I need to convert this logic signal to electric

The issue is that after L2E conversion I get the electric clock with a delay compared to the logic clock and that delay seem to be random each cycle (subject to simulation step) This adds a lot of phase error to the PLL input and finds its way to the output of the PLL.

I want cadence to somehow always get the electric clock to be as close as possible to the logic clock, something like within 10fs of it or at least have a fixed delay that is not changing with each cycle

I am using Spectre-X CX (highest accuracy) and I tried different connect-rules like rise/fall times to be as low as 10fs but does not seem to fix the issue. I tried APS as well but does not improve results

Any ideas how to fix this?

AMS/SimVision simulation

PE202503078250 — Tue, 21 Apr 2026 15:13:04 GMT

I simulated a verilog testbench with a module consisting of a synthesized gate level netlist in SimVision. It seems to be working (at least giving an output signal that looks valid)

However when I ran the same simulation in Cadence Virtuoso using the AMS simulator, the output seems to be in the High-Z/undefined state. Is there any simulation setting that I'm missing ? The testbench in Virtuoso doesnt have any analog blocks. All are verilog modules. So then I assume any setting mistakes related to the ConnectModules can be ruled out. However, the RTL code (of the corresponding gate level netlist) indeed works in Virtuoso.

simvision analog variables and signals display issue

mxgong — Wed, 25 Mar 2026 23:59:57 GMT

Hi,

I am running ams simulation in the interactive mode.

However, the simulation has gone through, but I can only observe the digital signals. All analog signals (including inputs and outputs) and variables within the analog begin block are showing no value in the waveform window.

Here vin[8] is a net in the testbench schematic. triggers_out[x] are digital signals. Ceq is a real number inside the analog begin block.

When I stop the simulation and open result browser, the signals in schematics are saved there.

Thanks

Minxiang

RE: simvision analog variables and signals display issue

Andrew Beckett — Fri, 03 Apr 2026 11:24:01 GMT

[quote userid="573754" url="~/cadence_technology_forums/f/mixed-signal-design/65873/simvision-analog-variables-and-signals-display-issue/1408175"]The previous one that worked with udb is using XCELIUM 64b 20.09-s009 and Spectre 64b 21.1.0.648.[/quote]

This worked before, then something broke, and as far as I know it's been fixed in the meantime. Hence my suggestion to use a later version (I'm just not sure whether it's on the XCELIUM or SPECTRE side - I would have to do some digging for that and I'm away from work for a few days...)

Andrew

RE: simvision analog variables and signals display issue

mxgong — Thu, 02 Apr 2026 17:22:15 GMT

The previous one that worked with udb is using XCELIUM 64b 20.09-s009 and Spectre 64b 21.1.0.648.

Minxiang

RE: simvision analog variables and signals display issue

Andrew Beckett — Thu, 02 Apr 2026 16:12:19 GMT

Can you try with a more recent version of both XCELIUM and Spectre? There were some UDB-related issues with waveform display (without knowing the precise details it's hard for me to check what broke when and was fixed when).

Andrew

RE: simvision analog variables and signals display issue

mxgong — Wed, 01 Apr 2026 18:40:28 GMT

If I change data format of spectre from udb to sst2. It works. I know simvision uses sst2 format, but I take a look in udb option that it did save the data in sst2. I have to manually reload database in simvision. Any root cause of this?

RE: simvision analog variables and signals display issue

mxgong — Thu, 26 Mar 2026 16:11:42 GMT

Hi Andrew,

Thanks for the quick reply.

the XCELIUM version is 23.03-a071 64b

the spectre version is 24.1.0.314.isr6 64b

Thanks

Minxiang

RE: simvision analog variables and signals display issue

Andrew Beckett — Thu, 26 Mar 2026 13:49:45 GMT

Minxiang,

Which XCELIUM and SPECTRE sub-versions are you using? (these will be reported in the simulation log)

Andrew

RE: Calling AMS control file in ADE AMS Simulations

Saloni Chhabra — Tue, 17 Feb 2026 17:05:32 GMT

You can include it through Options -> AMS Simulator -> Include Option Settings -> Include Options (tab) -> Files on xrun command line

Saloni

Calling AMS control file in ADE AMS Simulations

Cherrihane — Mon, 16 Feb 2026 22:44:30 GMT

I created an ams control file amscf.scs and added an amsd block within it. I want to use this file in my AMS simulations, how can i included it in ADE?

Replacing cell in an analog on top testbench by an external HDL module that has different name

Cherrihane — Mon, 16 Feb 2026 22:41:31 GMT

I have an analog-on-top testbench and would like to replace a specific cell with a digital module. The digital module and its submodules are defined in external files without existing cell views. I have included these files via Simulation > Options > AMS Simulator > Include Option Settings.

However, the top module name in the Verilog file differs from the name of the cell view I am replacing. How can I configure the mapping so the tool replaces this cell with the provided Verilog module file?

I am using AMS designer through ADE GUI (AVUM flow)

RE: Replacing cell in an analog on top testbench by an external HDL module that has different name

Kevin T Buck — Tue, 17 Feb 2026 16:53:33 GMT

As far as I'm aware I don't think this is possible. You could generate a wrapper cell with the same name and instantiate your verilog block within the wrapper to work around this.

RE: AMS Connect module

SH202507179147 — Fri, 13 Feb 2026 05:59:35 GMT

Im not sure of R2E and E2R, but I have got L2E and E2L.
can we do custom model for R2E and E2R?

AMS Connect module

SH202507179147 — Thu, 12 Feb 2026 12:10:34 GMT

Im new to AMS-Verification.
I have modeled differential amplifier in VAMS.
Now I want to verify it using RNM. Have created a RNM-TB and connectmodule too, for electrical to real and real to electrical.
but im getting error in connectmodule.

What should be included in connectmodule:
input, output, electrical: must
real, wreal?

`include "disciplines.vams"

//real to electrical; for stimulus conversion
connectmodule real_to_ele ( vin_r, vin_e);
input vin_r;
output vin_e;
real vin_r;
electrical vin_e;
analog begin
V(vin_e) <+ vin_r ;
end
endmodule

//electrical to real; for observing the output
connectmodule elec_to_real( vout_e, vout_r);
input vout_e;
output vout_r;
electrical vout_e;
real vout_r;
analog begin
vout_r = V(vout_e);
end
endmodule

RE: AMS Connect module

tpylant — Thu, 12 Feb 2026 22:28:13 GMT

There are R2E and E2R connectmodules that ship with the Cadence install. Have you looked at using those?

Tim