I'm using DE HDL with constraint manager. There are two buses in the schematic, Data<31..0> and ADDR<12..0>. When I launched Constraint Manager, in ther Net worksheet, Constraint Manager recognised Data and ADDR as bus objects, but there was just one bit under the ADDR bus, ADDR<0>, other bits ADDR<1> to ADD<12> were missing.
I tried to modify the .dcf file in the constraints directory, and add the ADD<1>--ADD<12> manully to the ADD bus. After the design was packaged, they were still missing.
Please give me some advice to fix this and how this happened.
I found what the problem was. The ADD bus termination to the same reference voltage make the Constraint Manager assume it was an XNet.
Now, the new question is how to manage this type of topology to maintain the bus?
I can not upload the image. You can see it through the link below:
The problem have been solved.
So how did you resolve this?