I'm starting with my first layout (master thesis: rf frontend) in Cadence SPB 15.7 and have a lot of questions. Here are some of them:
1.) Before I start with the schematic, I think I have to create the schematic-symbols and the footprints of the ICs. I already followed a tutorial which showed how to make the padstacks and the footprints with assembly outline, silkscreen outline, package boundary. I startet with an easy footprint of the MAX4447 with SOIC 16 pins. But I have no tutorial which explains how to create the schematic-symbol and how to link it with my new footprint. Any idea where to find one?
2.) The next parts, I have to create are TSSOP20, SOT-89, QFN-LP3, 20pin MCM, 56TQFN, SOT3, SOT-666, QFN-6.
It's a lot of work and I don't know if everything I do is correct. So are there downloadable footprint packages which contain some of my needed footprints? I think I have to compare every downloaded footprint with the datasheet of the part but it would speed up my work a lot.
3.) Any other hints? =)
Sorry i forget to attached the utility, here it is .......
Thank you for the link, I downloaded the tool a few minutes before your post and I think it will help me a lot.
I have Cadence SPB 15.7 with "Design Entry HDL". When I start "Design Entry HDL" I have the choice between:
"Allegro Design Entry HDL L"
"Allegro PCB Design HDL L"
"Allegro PCB Design HDL XL (PCB Design Expert)"
Who would start a master's thesis on an expired toolset? What university are you at? What is your thesis?