I have been trying to get this to work for us and eliminate any OFE (opportunity for error), the ability to see if the short is made at the logical view, ability to make sure the short was routed in the report (Summary Drawing Report), able to export to AnsoftLinks and able to provide DRC checking to non shorted nets. This is what I have done so far:
I created a 2 pin component consisting of simple round single layer pads and placed them on top of one another. We use SCM for our front end so when the component is added I add the NET_SHORT property to each pin and attach the appropriate values (AGND:GND and GND:AGND). Export Physical to my SiP design and when the component is placed there were no Pin to Pin Drc's and I have a rats nest showing, so far so good.
I can route into the pins from either net with no problems but I get a Line to Line DRC. Ideally we would like to have this "Net Short Component" placed and connected by over lapping shapes so the geometry can easily be modified to accomodate the particular layout (i.e. small connection for some and large areas for High Voltage designs). When I place the component and bring a shape over it from the 2 different nets I get Shape to Shape DRC's. I used the SHORTING_SCHEME property on the 2 different nets assuming this would eliminate my DRC's but that has not worked either.
This appears to be so close to working but I am not able to eliminate the DRC. Our company is regulated by FDA so we have to document each and every DRC in our designs so obviously we strive to have no "flase DRC's" within our designs.
Froom what I am reading in the Help files it would appear the NET_SHORT property would work by itself but since it did not it appeared to be logical to try the SHORTING_SCHEME in addition to the NET_SHORT but again that is not working.
Has anyone have this working with the requirements I have listed in my opening paragraph?