I need to find out acid trap in electrical layers.could u plz help me in 16.3V
The only option you have in 16.3 is to set the same_net_spacing rules to be the value you want and then look at the DRC list. You need to enable them in Constraint Manager - Same Net Spacing Constraint Set - Options, change from Flase to True plus set the values you want. The also under Analyze - Analysis Modes turn on the same net spacing modes. Probably just need to set Pin to Line.