Does anyone have any suggestions on creating footprint with thermal pad that requires topside via tenting on the top side?
I tried making shape symbols for solder mask/ paste mask, but due to the void in the shape it requires I am not able to create it.
I can place the shapes manually in package geo/ SM or PM, but I think lot of the data does not have it to display in the default setting for our filmsetting.
Please let me know if there is a way to make the shape symbols or not.
Thanks in advance.
I've been playing around with these footprints, and checking the actual gerber output to see if it agrees with what I'm seeing in Allegro. I'm still using 16.5, btw.
The primary issue I'm trying to raise lies with the provision that exists (in Padstack Designer) to put multiple drills into a padstack, even if it's "single layer mode". The problem is that those holes don't actually exist in any other layer except layer one. I get a really entertaining NC drill file for holes connecting layer 1 to layer 1 when I produce the manufacturing files. I'm thinking the "multiple drill" option should probably be grayed-out when in single-layer mode. (?)
If I make these padstacks multi-layer, and put pads on just the top and bottom of the board; there is a bounding rectangle created that attempts to surround them. The kick in the head is that the bounding rectangle isn't getting the x/y offset that's been specified for the multiple drill array, but is just centered within the padstack, and would be sized appropriately if the multiple drill was centered, too =/
(did I miss some critical configuration option that's causing this?)
This should clarify what I'm talking about, and the failure to align the clearance rectangle with the hole array:
I understand what you're saying about using a PCB for removing heat. The reality is that a number of manufacturers (like TI) are using packages that need to use the PCB as a heat-spreader, or as a thermal path to a heatsink proper. I suspect we'll probably be seeing more and more of this kind of stuff as the packages keep shrinking. The TI docs on that part in the "eTSSOP" package are pretty adamant about this being done, and they do put some numbers to the copper thickness and area size on the backside of the board, which suggests they have some faith in the ability of copper to work this way.