In our previous designs I would append a \\ to the end of a net alias to signify that it is active low. Example; OUTPUT ENABLE\\
Now I find that the "\\" is considered an illegal character so I have two questions
1. I'm open for suggestions as to a different approach on how to show that the net is active low within the net alias
2. Is there a way to catch these "illegal net names" in Capture before I go and import the logic into PCB Editor. I have run all sorts of error checking in capture and these nets do not come up as being problems.
There is currently no DRC for illegal net names. (Talk to your VAR and put in an enhancement request). With 16.6 there are custom DRCs so you might be able to write on using Tcl/Tk.
The \O\E works for pin names but not net names. You could use _H, _L or _P, _N as alternative netnames (Again raise an enhancement request with your VAR).
try setting the allegro environment variable legacy_character_set. You can find it in the environment editor (enved)
fxffxf said: try setting the allegro environment variable legacy_character_set. You can find it in the environment editor (enved)
That works like a champ!
That little check box just saved me tons of work!