Hi, I saw people make schematic symbol for a complex FPGA(almost 400 pins), and that schematic break one FPGA into many different pages. Like bank1 at the first page, bank 2 at the second page,etc.How to build a multi symbols FPGA?
Go with what works best for your design flow. I have found that it is useful in many circumstances to make a separate symbol for each bank and include the VCC/GND for that bank in that block. More than 50-75 pins per block can be cumbersome on a schematic unless you have some grouped busses for example.
The first thing I do is convert the datasheet pinlist to a text file using Adobe or some PDF reader. In some circumstances the FPGA vendor will supply an Excel pinlist -- just ask.
Once you have the pinlist you can quickly use the OrCAD spreadsheet editor to place the pins in each block. You want to have heterogenous part selected and predetermine how many blocks you want. In the spreadsheet editor you can choose which block the pin goes and what type of pin it is (input, output, bidir, 3state).
Once the spreadsheet is completed you can review the symbols and move pins as required for better schematic connectivity.
Think about how to manage pinswapping in the future --- that is a very powerful and necessary feature of FPGAs. Read up on that.
Hope that starts you off.
That really helpful~~Thank you so much.
Last Friday, I did a hand typing a 96 pins BGA. It take me a few hours and many typing errors~~
This is very very very good idea
I do my FPGAs the same way as redwire except I put all the power and gnds in a power section to unclutter the signal sections. It is a good way to do symbols for FPGAs.
VincentS said:I do my FPGAs the same way as redwire except I put all the power and gnds in a power section to unclutter the signal sections. It is a good way to do symbols for FPGAs.
The only time I manually type in pin names is on something with fewer than 6 pins.
Check out the EDABuilder app from EMA-EDA.
Zero retyping... From either the Altera BSM file or a spreadsheet.
Extracted the pinmap for Intel's 2011-pin Pentium package recently from their datasheet PDF.
And, their footprint builder rocks too.
Only thing easier is to let the Cadence FPGA planner dynamically manage pin assignments.
Safer to split the FPGA up by banks and include the pin-driver power of that bank. If you're dealing with a mix of 1.8v, 2.5v, and 3.3v logic, prevents goofs.