In my develop board there has a DIMM connecter,i will simulate the board with the Dimm board,but i have the DIMM board ebd file,i have translated the ebd file into boardmodle file? how can i use the boardmodle? i can not assign the boardmodle to the DIMM connecter? can you tell me the next step? thanks !
You need to use Designlink to link with your boardmodel. To do so, in PCB SI, click Analyze->SI/EMI Sim->Initialize... Singal Analysis Initialization dialog will be shown. Click New DesignLink Button to set up. Hope this helps, Lance
lwang: Thanks you help! The step you tell me i have tried,i have created the designlink ,but i can not get the topology by using Cmgr.and there is a messsage displaying. the follow is the message "" WARNINGS: WARNING: You are extracting from a BoardModel and will not get the correct interconnect data in SigXp. The Allegro PCB SI product does not fully support BoardModel extraction in this release. While the buffer models are correct, the BoardModel interconnect is not. Be sure to delete the interconnect and redraw it to reflect the interconnect contained in your BoardModel "" can you help me ? thanks by the way ,canyou tell me your email?
This is known problem. The reason is that the topology shown in SigXp doesn't contain the correct interconnects in the boardmodel. However, if you simulate them in the SQ(PCB SI, not SigXp), the result is correct. The issue only exists in the SigXp. My email is email@example.com. Be free to send the questions to me directly. Lance
lwang: i find when i use .dml file which directly come from manufacturer,i can get the topology. but the file which i translated from .ebd file can not get? can you tell me the reason? And not all topology can not get.for example, i can get the ddr address signals topology,but the data signals can not
I would believe that EBD should be translated to DML before link to Designlink. It means after EBD translated to DML then both DML boradmodels should be the same. So, you should be able to extract them to SigXp on both cases. But as I mentioned before, I don't think the interconnects in the boradmodel partion are correct. Please check them againest to BoradModel file (DML or EBD). Hope this helps. Lance