RAVEL DRC Programming for IC Packaging and PCB - Recent Threads

RE: Download Ravel Standard Library

shawnpatel — Wed, 05 Oct 2022 14:21:58 GMT

Hi Björn, thanks for the reply. We've gone through those internal channels and have gotten it, thanks!

Download Ravel Standard Library

shawnpatel — Thu, 08 Sep 2022 18:40:00 GMT

Where can I download the Ravel Stardard Library? I see how to install it once the software package is downloaded, but where is the software package hosted?

RE: Download Ravel Standard Library

Bjoern L — Wed, 05 Oct 2022 12:37:53 GMT

Hi,

the RAVEL Standard Library is made available to customers that have the appropriate products for doing RAVEL development. Please contact me directly at bjorn@cadence.com.

Best regards,

Björn Lindberg

RE: fiducial holes creation

BinduSripad — Mon, 17 Dec 2018 08:39:52 GMT

Hi Babu,

Please post this question in the PCB design forum:

https://community.cadence.com/cadence_technology_forums/f/pcb-design

This is no provision to create fiducial symbols using Ravel language.

Thanks,

Bindu

fiducial holes creation

babu pcb — Tue, 11 Dec 2018 10:12:26 GMT

hi to all ,how to create fiducial symbols in allegro,i am new to allegro and i got stuck in fiducial symbol creation.is fiducial symbols are created using mechanical symbol option?or not.if it is right then how to give copper pad and clearance to the circles.

Welcome to the RAVEL forum!

admin — Thu, 01 Aug 2013 19:19:01 GMT

This forum is intended as a meeting place for discussions and exchanges on the broader theme of writing programs in the RAVEL DRC language for IC packaging and PCB. Topics related to the RAVEL engine and compiler, or how RAVEL integrates and is used in an environment or flow are also welcome.

This is the place to ask questions or share ideas with other RAVEL users.

RE: Welcome to the RAVEL forum!

kumarsanj — Mon, 17 Sep 2018 05:46:05 GMT

Thank you Bindu.

Regards,

Sanjeev

RE: Welcome to the RAVEL forum!

BinduSripad — Wed, 12 Sep 2018 05:22:35 GMT

Hi Sanjeev,

Please find the link to Ravel reference manual here:

Ravel Language Reference Manual

Pointers to writing macros in Ravel:

Macros in Ravel

If you have any specific questions, please file a service request and it will answered at the earliest.

Thanks,

Bindu

RE: Welcome to the RAVEL forum!

kumarsanj — Mon, 10 Sep 2018 16:03:11 GMT

Can we get a link of RAVEL document?

Thanks,

Sanjeev

RE: Ravel DRC makrer on dielectric layer

Ze Lyu — Fri, 29 Jun 2018 17:36:14 GMT

I got it work thanks man!

Ravel DRC makrer on dielectric layer

Ze Lyu — Tue, 26 Jun 2018 17:55:27 GMT

I am trying to write some DRC script for vias(drills) in different dielectric layers. However, I am not able to place the DRC makers on the dielectric layers where the targeted via drills locate. I only know how to place them in conductor layers or just by default, through all layers. but that's not what I wanted at all. Is there anyway to accomplish this?

Thanks,

May the force be with y'all,

Zee

RE: Ravel DRC makrer on dielectric layer

Bjoern L — Fri, 29 Jun 2018 16:16:33 GMT

Hi Zee,

in order to be able to draw on a dielectric layer, it has to be named. If you open the Cross Section Editor, you should see a name for each such dielectric layer, just like the conducting layers have names. That is the name that you would give as a string.

Regards,

Björn

RE: Ravel DRC makrer on dielectric layer

Ze Lyu — Fri, 29 Jun 2018 15:37:22 GMT

Hi Björn ,

Thanks for your response! I am not what string to put in as dielectric layer name. Could you give me an example?

May the force be with you,

Zee

RE: Ravel DRC makrer on dielectric layer

Bjoern L — Fri, 29 Jun 2018 07:53:17 GMT

Hi Zee,

There are two ways of specifying the layer for a marker: either giving the top layer separation of the layer as a number, or giving the layer name as a string. The first method is not possible for named dielectric layers, because top layer separation only applies to conducting layers, the second method would however be possible; you can give the layer name as a string in the violation statement. If you have many such layers, this could turn out to be slightly inconvenient, since you would need one violation statement per layer. There is a planned enhancement to allow specifying the layer in the form of a stack_layer object. This would make it possible to place markers on parameterized named dielectric layers by combining the violating objects with stack layers and selecting for same layer. Please let me know if the method of specifying the layer name as a string is sufficient to solve your problem, or if you would profit from the planned enhancement I described.

Regards,

Björn Lindberg

RE: How Can I Get the Max. Length of all wires on a design ?

BinduSripad — Tue, 03 Apr 2018 06:07:55 GMT

Hi Kenjung,

Sorry, CHOOSE_MAX macro calls some other macros that I did not share.

Please use the following code to find the longest wire in the design:

(macro CHOOSE_MAX_LENGTH (Object Measure)
(difference Object
(transform (o1 o2)
(select (o1 o2) (combine Object Object)
((length o1) > (length o2)))
(o2))))

(define longest_wire
(transform (w)
(CHOOSE_MAX_LENGTH wire length)
(w (length w))))

The macro finds the shorter of two wires and subtracts it from the relation containing all the wires. When done in iteration, this leaves us the wire with maximum length.

The same macro can be altered to pick the wire with shortest length. You only have to change this line in the macro to find the shorter of two wires:

((length o1) < (length o2))

Thanks,

Bindu

How Can I Get the Max. Length of all wires on a design ?

Kenjung Chang — Fri, 30 Mar 2018 07:14:32 GMT

How Can I Get the Max. Length of all wires on a design ?
the (max) function only judges two numbers, but I have to get the max. value of a relation.

(transform (w) wire (w (length w)))

RE: How Can I Get the Max. Length of all wires on a design ?

Kenjung Chang — Fri, 30 Mar 2018 10:26:44 GMT

Hi, Bindu :

Thanks for your reply, but I can't find any standard library path including "standard/basic" .
Can you tell me the absolute path (in APD 16.6) of the standard library path ?
And, is there any manual about these functions such as <CHOOSE_MAX> or <CHOOSE> .

Further more, I can't understand too, the following instruction.
Is this means I can define a macro named "CHOOSE_MAX" myself?
But I don't see any code or method here.
-------------------------------------------------------------------------------------------------------------------

if you do not have the standard library files, please use the following macro:

(macro CHOOSE_MAX (Object Measure)
"CHOOSE_MAX [object] function/measurement => [object]

------------------------------------------------------------------------------------------------------------------

RE: How Can I Get the Max. Length of all wires on a design ?

BinduSripad — Fri, 30 Mar 2018 08:52:57 GMT

Hi Kenjung,

If you have access to Ravel Standard Library, please use the following code:

(include "standard/basic")

(define longest_wire

(transform (w)

(CHOOSE_MAX wire length)

(w (length w))))

if you do not have the standard library files, please use the following macro:

(macro CHOOSE_MAX (Object Measure)
"CHOOSE_MAX [object] function/measurement => [object]

Find the object for which the measurement is smallest. If the objects
themselves are the values to be compared, IDENTITY can be given as
the measurement function."
(CHOOSE Object greaterp Measure))

Thanks,

Bindu

RE: Setup RAVEL

comet — Fri, 24 Feb 2017 05:56:05 GMT

Oh yeah, i checked my env and the DFM_RAV_PATH wasn't called. I had used an old file. Thanks again. ;-)

Setup RAVEL

comet — Fri, 24 Feb 2017 02:48:33 GMT

Hi Guys,

I couldn't run RAVEL under Allegro PCB Designer Manufacture tab. It prompted "Environment Variable DFM_RAV_PATH is not set. Please set it to the correct path and try again."

Please let me know how.

Thanks! ;-)

RE: Setup RAVEL

BinduSripad — Fri, 24 Feb 2017 05:51:35 GMT

Correction:

Please type

setup dfm_rav_path c:/cadence/spb_17.2/share/pcb/dfm_ravel

RE: Setup RAVEL

BinduSripad — Fri, 24 Feb 2017 05:46:13 GMT

Please type the following in your Allegro Command Window (assuming you are using Allegro 17.2 and Cadence installation directory is c:/cadence):

set dfm-rav_path c:/cadence/spb_17.2/share/pcb/dfm_ravel

Thanks,
Bindu

RE: Setup RAVEL

comet — Fri, 24 Feb 2017 05:37:59 GMT

Hi Bindu, where and how can I set the DFM_RAV_PATH?

RE: Setup RAVEL

BinduSripad — Fri, 24 Feb 2017 03:45:32 GMT

Hi,

Please set your DFM_RAV_PATH to c:/cadence/spb_17.2/share/pcb/dfm_ravel or c:/cadence/spb_16.6/share/pcb/dfm_ravel (based on where your Cadence installation folder is) and try again.

Thanks,
Bindu

Best way to determine pad pitch

GMaggy — Wed, 11 May 2016 14:16:34 GMT

What is the best way to find the pad pitch when the design has 27000+ pads? Using the (combine relation1 relation2) operator crashes my session as Ravel attempts to store 729 million+ combinations. Even if I break the design into quadrants to reduce the number of pads being looked at, Ravel still has to deal with 48 million+ combinations. Also, looking only at the pads nearest the design edge doesn't give me the result I'm looking for. I need to find the minimum pad pitch in the design.

Do you have any suggestions?