RF Design - Recent Threads

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

Tawna — Thu, 02 Apr 2026 17:59:17 GMT

If simulating pnoise sampled(jitter), set the pnoise stop frequency to 1/2 pss_fundamental. There are a couple of articles that mention this:

How can I set the stop frequency for a sampled pnoise/hbnoise analysis to be half the PSS fundamental?

The mathematics behind choosing the upper frequency when simulating pnoise jitter on an oscillator

If simulating a divider or multiplier, follow the guidelines here:

How to set up pss/pnoise sampled(jitter) when simulating a driven circuit or a VCO, both containing dividers

How to simulate a Frequency Multiplier (x2) in SpectreRF Shooting Newton PSS

PNOISE Noise Type Time Average vs. Sampled Jitter

AB_1719406998389 — Mon, 30 Mar 2026 20:39:07 GMT

I am new to the sampled jitter noise type in Pnoise simulation and I want to compare the results between time average and sampled jitter settings. My testbench is very simple, a square wave input at 8G and a 4 stage differential inverter buffer. The fanout ratio is 2 and I am looking at the differential noise at the output of stage 1,2 and 3. The otuputs are all square wave-ish. The time-domain waveform at input and stage 1,2,3 outputs are as following snapshot.

Then I started to compare noise results. Here I compare the differential noise at stage 1,2,3 output, in two forms. The first is the output noise (dBc/Hz) - PM - DSB with time average setting. The second is the edge phase noise (dBc/Hz) with sampled jitter. The trigger is at the rising edge of the the difference between the differential signals and set at when it crosses zero. I found the noise results between these two settings are very similar. They are attached at the following snapshot. The solid lines are results from time average, the dashed are from sampled jitter. The graphes from left to right are results at stage 1,2 and 3 output.

My understanding is like this. For buffers with sharper edges, most of the noise is phase noise and the crossing point has the worst jitter, or phase noise. In that case, the time average and sample jitter should give similar results. If the edges are not that sharp, then sampled jitter should give worse results as it is really looking at the worst point while time average should give better results as it is averaged within a cycle. But here sampled jitter seems to give a phase noise similar to a DSB output noise from time average. So result from sampled jitter is 3dB worse if we are talking about phase noise as it is defined as SSB. This is very confusing for me, especially it is almost exactly 3dB. Can any one help me to point out if I am mixing different things? or the way to understand the edge phase noise result from sampled jitter setting. Thanks!

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

Tawna — Thu, 02 Apr 2026 17:21:00 GMT

Thank you, Janko, for your responses.

To the original poster: You may also want to look at this Article Pnoise/hbnoise: Frequently asked questions on https://support.cadence.com. It contains important information on the various pnoise/hbnoise settings and how to determine when your simulation result is accurate.

Best regards,

Tawna

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

AB_1719406998389 — Thu, 02 Apr 2026 12:40:46 GMT

thanks for the message.

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

JankoK — Tue, 31 Mar 2026 14:42:09 GMT

By the way, if you are using our standard expressions (from Direct Plot) for Phase Noise (time averaged) and Edge Phase Noise (sampled), they are both SSB. If you are to run transient and do PN() you would end up with DSB. Then you would need to subtract or add 3.01dB to get the matching.

/Janko

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

JankoK — Tue, 31 Mar 2026 09:22:36 GMT

Yes, 50 is more than enough... with 8.4G frequency, 100G noisefmax equivalent would be like 12 harmonics.

Looking at you setup... your stop frequency is too low. You are cutting 3/4 of contributors. It should be 4.2G (half fundamental). There used to be an article that explains the reasoning but its being revoked for updating. There is this one that mentions it:

How to reconcile the linear noise, pnoise, and transient noise results on a switched capacitor ckt?

The rest seems ok to me.

/Janko

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

AB_1719406998389 — Tue, 31 Mar 2026 08:58:11 GMT

thanks again for your help

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

AB_1719406998389 — Tue, 31 Mar 2026 08:57:00 GMT

Hi Janko

Thanks for your message!

Sorry forgot to include in the post that noise at rising edge and falling edge are very similar. For noisefmax, I put a harmonic of 50 in the PSS setup so that should cover beyond 400G. The snapshot of my PSS, timeaverage Pnoise and sampled jitter Pnoise is as following snapshot.

RE: PNOISE Noise Type Time Average vs. Sampled Jitter

JankoK — Tue, 31 Mar 2026 08:15:14 GMT

Hi,

Note that with noisetype=timeaverage, you are averaging across the whole cycle, both states and both edges. On the other hand, with noisetype=sampled, you are measuring at that specific threshold point of rising edge. Perhaps falling edge carries more noise in your case. You should plot that one too for fair comparison. There is a nice article that covers this:

Why is pnoise sampled(jitter) different than pnoise timeaverage on a driven circuit?

If that's not the case, you should perhaps revisit your setup. Abrupt edges in combination with high frequency sometimes require very high noisefmax (and even number of harmonics/sidebands) for accurate results. As a rule of thumb, you can use 1/risetime as a starting point, which ends up being around 100G in your case. Start there and then increase it until you see no changes in your noise results.

Hope this helps!

/Janko

RE: Spectre netlist defining voltage gain and saving the results to view in the psf file

Andrew Beckett — Mon, 26 Jan 2026 16:53:45 GMT

Or simpler still:

VpOUT (OUT 0 OUTP OUTN) vcvs gain=1

Note that ViVA can also plot differential signals without needing to use the calculator.

Andrew

Spectre netlist defining voltage gain and saving the results to view in the psf file

GM202510215619 — Thu, 22 Jan 2026 16:41:51 GMT

Hello, I have a simple circuit with Vout as the output node of the amplifier and Vin as the input node of the amplifier.

I want to save the dB voltage gain results and plot it in ViVA from the raw file.

Is there a way to do it through using a few lines of code in my spectre testbench netlist?

Any help would be appreciated. Thank you

-GGM

RE: Spectre netlist defining voltage gain and saving the results to view in the psf file

GM202510215619 — Mon, 26 Jan 2026 14:01:17 GMT

Thanks so much for the quick answers. I was able to get the transfer gain using both methods. I was wondering if there's a way to save differential voltage without using calc in ViVA. The method I am using now is something like:

VpOUT (OUT 0) bsource v=v(OUTP, OUTN)

Then node OUT is saved as differential voltage.

I might be missing a simple way to do the same.

RE: Spectre netlist defining voltage gain and saving the results to view in the psf file

Andrew Beckett — Sun, 25 Jan 2026 12:05:04 GMT

The output of an xf analysis can certainly be differential. If the input is a single voltage source (across a differential input, biased somehow) then you could use xf analysis. Or you could use ac analysis and have two input sources each with (say) mag=0.5 (phase set appropriate or one source inverted) and then plot the output voltage in the ac results between the two output nodes.

Andrew

RE: Spectre netlist defining voltage gain and saving the results to view in the psf file

GM202510215619 — Sun, 25 Jan 2026 08:29:57 GMT

Is this also the way to do it for differential nodes?

RE: Spectre netlist defining voltage gain and saving the results to view in the psf file

Andrew Beckett — Thu, 22 Jan 2026 17:28:18 GMT

If you want small-signal gain, you could use an xf analysis:

xf (Vout 0) xf start=1 stop=1G

Then in the xf results, you'll see listed all the voltage sources in the circuit. Assuming there's one which is connected to the Vin signal, you can set the results browser to plot in dB20 (it will show Default and Magnitude at the top of the results browser; change the Magnitude to dB20). Double click on the voltage source and you'll get the gain in dB.

Andrew

RE: P+ diffusion resistor with salicide (3 terminal)

SamanMKD — Wed, 10 Dec 2025 01:26:40 GMT

Dear Andrew,

Thanks for your reply. I am using 28nm HPCP PDK. I created a N-WELL contact as you mentioned and it fixed the connectivity issue and DRC errors.

P+ diffusion resistor with salicide (3 terminal)

SamanMKD — Tue, 09 Dec 2025 12:16:42 GMT

Hello everybody,

In order to use "P+ diffusion resistor with salicide (3 terminal)" in my design, how can I connect the Bulk (N-Well) to VDD (metal 8)?

Best,

RE: P+ diffusion resistor with salicide (3 terminal)

Andrew Beckett — Tue, 09 Dec 2025 19:03:36 GMT

You didn't mention which PDK this was but presumably you'd need to create an N Well contact and then a stack of vias up to Metal 8. That seems fairly obvious, but maybe I'm missing something here?

Clarity menu in Virtuoso

ArbLouis — Tue, 18 Nov 2025 15:06:59 GMT

Hi everyone,

I have installed Clarity 2024 (SIGRITY 2024.1) and I am using Virtuoso IC23.1 on RHEL9.

I can successfully run Clarity as a standalone application (Layout Workbench), so the installation path and license seem correct. However, I cannot see any Clarity/Sigrity menu inside Virtuoso Layout, even when switching to the "Electromagnetic" workspace.

Here is the configuration I added to my .cshrc file:

# 1. Fundamental Root Variable
setenv SIGRITY_EDA_DIR /home/EDA/cadence/IC_23/SIGRITY20241
# 2. Compatibility Variable
setenv CNI_ROOT $SIGRITY_EDA_DIR
# 3. Update PATH (Note: tools.lnx86 is essential here)
set path = ( $SIGRITY_EDA_DIR/tools.lnx86/bin $SIGRITY_EDA_DIR/tools/bin $path )

Is there a specific SKILL script I need to load manually in my .cdsinit for the 2024 version, or is there an installation script in the bin folder I missed?

Thanks in advance for your help.

I've used this guide: Virtuoso RF Solution Package Electromagnetic Simulation Rapid Adoption Kit (RAK) Product Version: IC23.1 July 2023

LoapPull Analysis For Differential Power Amplifier

RM202501276525 — Mon, 10 Nov 2025 08:34:09 GMT

Is using a VCVS to convert the differential output to single-ended the correct way to perform a load pull on a differential power amplifier?

---- Cannot upload pictures onto the website.

RE: LoapPull Analysis For Differential Power Amplifier

RM202501276525 — Mon, 10 Nov 2025 11:53:38 GMT

When I use the ideal_balun_p2s from analogLib to convert my differential output to a single-ended signal for the load port, the simulation fails during the initial DC convergence for every sweep point.

I receive this error.

Warning from spectre at theta = 359 during IC analysis, during periodic steady state analysis `lppssrho-010_lppssphi-020_pss', in `lppssrho-010_lppssphi', during Sweep analysis `lppssrho'.
WARNING (SPECTRE-16001): Sweep iteration for `theta' = 359 terminated prematurely because of the following error(s):
Error found by spectre at theta = 359 during IC analysis, during periodic steady state analysis `lppssrho-010_lppssphi-020_pss', in `lppssrho-010_lppssphi', during Sweep analysis `lppssrho'.
ERROR (SPECTRE-11006): Matrix is singular (detected at `L2:1' and `I9.K1:t1').
ERROR (SPECTRE-16080): No DC solution found (no convergence).

The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol

Top 10 Residue too large Convergence failure:
I(V0:p) = 0 A
residue too large: | 2 V | > 10 mV + 1 uV
I(V1:p) = 0 A
residue too large: | 450 mV | > 2.25 mV + 1 uV

The following set of suggestions might help you avoid convergence difficulties. After you have a solution, write it to a nodeset file by using the `write' parameter, and read it back in on subsequent simulations by using the `readns' parameter.

1. Evaluate and resolve any notice, warning, or error messages.
2. Perform sanity check on the parameter values by using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value by using `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

3. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

4. Enable diagnostic messages by setting option `diagnose=detailed'.
5. Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
6. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file, and set as many nodes as possible.
7. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
8. If simulating a bipolar analog circuit, ensure that the region parameter on all transistors and diodes is set correctly.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Increase the value of gmin (on options statement).
11. Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to a value in the range of 0.1 to 0.5 by using `pivrel' (on options statement).
12. Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model.
13. Divide the circuit into smaller pieces and simulate them individually. However, ensure that the results are close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit.
14. Check the connections to ground. Convergence problems might result if no connections to ground.
15. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when none of the signals in the circuit are changing) and write the final point to a nodeset file. To make transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach fails or is very slow because the circuit contains an oscillator. Often, for finding the dc solution, the oscillation can be eliminated for by setting the minimum capacitance from each node to ground (`cmin') to a large value.

Analysis `lppssrho-010_lppssphi-020_pss' was terminated prematurely due to an error.

**** Run Status for sweep analysis `lppssrho-010_lppssphi' ****
Sweep iteration 1 (`theta' = 0) failed.
Sweep iteration 2 (`theta' = 17.95) failed.
Sweep iteration 3 (`theta' = 35.9) failed.
Sweep iteration 4 (`theta' = 53.85) failed.
Sweep iteration 5 (`theta' = 71.8) failed.
Sweep iteration 6 (`theta' = 89.75) failed.
Sweep iteration 7 (`theta' = 107.7) failed.
Sweep iteration 8 (`theta' = 125.65) failed.
Sweep iteration 9 (`theta' = 143.6) failed.
Sweep iteration 10 (`theta' = 161.55) failed.
Sweep iteration 11 (`theta' = 179.5) failed.
Sweep iteration 12 (`theta' = 197.45) failed.
Sweep iteration 13 (`theta' = 215.4) failed.
Sweep iteration 14 (`theta' = 233.35) failed.
Sweep iteration 15 (`theta' = 251.3) failed.
Sweep iteration 16 (`theta' = 269.25) failed.
Sweep iteration 17 (`theta' = 287.2) failed.
Sweep iteration 18 (`theta' = 305.15) failed.
Sweep iteration 19 (`theta' = 323.1) failed.
Sweep iteration 20 (`theta' = 341.05) failed.
Sweep iteration 21 (`theta' = 359) failed.
Total time required for sweep analysis `lppssrho-010_lppssphi': CPU = 496 ms, elapsed = 677.585 ms.
Time accumulated: CPU = 8.36 s, elapsed = 10.4121 s.
Peak resident memory used = 134 Mbytes.

**** Run Status for sweep analysis `lppssrho' ****
Sweep iteration 1 (`mag' = 0) failed.
Sweep iteration 2 (`mag' = 0.095) failed.
Sweep iteration 3 (`mag' = 0.19) failed.
Sweep iteration 4 (`mag' = 0.285) failed.
Sweep iteration 5 (`mag' = 0.38) failed.
Sweep iteration 6 (`mag' = 0.475) failed.
Sweep iteration 7 (`mag' = 0.57) failed.
Sweep iteration 8 (`mag' = 0.665) failed.
Sweep iteration 9 (`mag' = 0.76) failed.
Sweep iteration 10 (`mag' = 0.855) failed.
Sweep iteration 11 (`mag' = 0.95) failed.
Total time required for loadpull analysis `lppss': CPU = 5.608 s, elapsed = 7.56544 s.
Time accumulated: CPU = 8.368 s, elapsed = 10.4204 s.
Peak resident memory used = 134 Mbytes.

modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.

RE: LoapPull Analysis For Differential Power Amplifier

Andrew Beckett — Mon, 10 Nov 2025 10:51:23 GMT

Perhaps you should use the ideal_balun from analogLib instead? Using a vcvs will isolate the load which is not what you want...

Andrew

cross coupled oscillator design problem

CC202509218347 — Sun, 21 Sep 2025 18:27:30 GMT

Hello everyone,

I'm currently working on the design of a cross-coupled oscillator, based on the circuit architecture shown in the attached figure (from a referenced paper). The resonator has a center frequency of 2.49 GHz, with C0 = 0.98 pF.

One of the key challenges I’m facing is ringing, which appears to be caused by the negative capacitance effects introduced by Csp and CHPF. In order to suppress this ringing, I attempted to ensure that the loop gain is less than 1 at the ringing frequency. However, this makes it difficult to simultaneously satisfy both of the following conditions:

Loop gain > 1 at 2.49 GHz
Loop gain < 1 at the ringing frequency

Simulation Setup:

For loop gain analysis, I used the STB (stability) analysis with an iprobe placed at the gate of M2.
For analyzing negative impedance and capacitance, I ran AC simulations by placing a current source across the output nodes and calculating the real and imaginary parts of the resulting impedance.

I would appreciate any suggestions or insights on simulation techniques and design strategies that could help with this issue.

source : B. Bahr, D. Griffith, A. Kiaei, T. Tsai, R. Smith and B. Haroun, "Class-C BAW Oscillator Achieving a Close-in FOM of 206.5dB at 1kHz with Optimal Tuning for Narrowband Wireless Systems," 2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Denver, CO, USA, 2022, pp. 311-314, doi: 10.1109/RFIC54546.2022.9863092. keywords: {Wireless communication;Phase noise;Performance evaluation;Micromechanical devices;Radiofrequency integrated circuits;Oscillators;Tuning;BAW;MEMS;Oscillator;resonators},

Re: How to get all data from srrWave？

EA202509149412 — Mon, 15 Sep 2025 07:21:08 GMT

Hello! I designed a PA and performed load pull on it. In the obtained constant power contour plot, I want to extract the data of the constant power lines on the Smith chart. I can normally extract the required data (X, YRe, YReImag) using 'send to export'. I wish to extract this data through code.

I use the code

line = leafValue( cPwrContour(i("/I1/out" ?result "hb_fd" ) v("/net7" ?result "hb_fd") '1 ?refImp 50.0 ?numCont 11 ?modifier "dBm") "p" 9.4631312)

and get the reply from CIW that :

srrWave: 0x5d9b5de0

I want get data from this srrWave, I use the code

ocnPrint(line)

but I get the result data (X, |Y|). Obviously, I could't get the phase from this data which I need. The output data type of the waveform should be Impedance, but it actually outputs Rectangular type. How can I get the data I need from this srrWave?

Integrating the EMPro/ADC in cadence virtuoso environment

Tarique mohd — Thu, 11 Sep 2025 14:32:20 GMT

I would like to run EMPro and want to import EM results into Cadence for S-parameter and other analysis.

Is it possible to integrate High Frequency tools( like ADS, EMpro) in cadence virtuoso environment?

BR,

Tarique