Verification IP - Recent Threads

Asynchronous Reset Assertion

RT202601231753 — Thu, 26 Feb 2026 10:01:24 GMT

I am a beginner in FPV and I have a scenario. Active low reset is asynchronously asserted in my design. When doing formal property verification, after running the tcl file, that is after running the " analyze command", and doing reset analysis, I am able to see the "reset" is applied on the internal registers. But while writing property for it, it is giving me vacuous success/pass. Antecedent is not triggering.

The property I write for asynchronous reset. Does the JG FPV automatically assert the reset at first cycle and then deassert it after one cycle

property async_resetn_prop_chk;
@(negedge PRESETn)
!(PRESETn) |-> (reg_ctrl == 4'h0); // internal register
endproperty

Kindly suggest.

use avip (tba mode ) on pz2， warning CTL socket cannot execute control from HW and did not find scope axiMaster.vr_axi_master_bfm.ctl_socket ,and Stuck in “wait reset done”

FQ202507317042 — Wed, 08 Oct 2025 06:06:32 GMT

I want to use AXI VIP on PZ2 , According to the example，i have already complete to build bitfile and sim, Everything goes well

but on my design , warning CTL socket cannot execute control from HW and did not find scope axiMaster.vr_axi_master_bfm.ctl_socket ,and Stuck in “wait reset done”

What can I do to solve this problem

How to implement a basic clean read-write sequence in Specman? Is this approach correct?

AP202508036621 — Sun, 03 Aug 2025 08:54:53 GMT

Hi, I’m trying to write a simple read-write sequence in Specman using a BFM. I wrote the code below, but I’m unsure if it’s the correct and clean way to do it. I see many variations online, which confuses me.

The sequence grabs the driver, performs a write transaction, waits a random number of clocks, performs a read transaction at the same address, then releases the driver.

I don’t have access to Cadence tools to test this, so I would appreciate feedback on the correctness of the sequence, use of grab/ungrab, and any improvements or best practices you can suggest.

Also, how can I run or simulate this without a Cadence license?

Thanks in advance!

**Code:**

    // READ-WRITE Sequence
    struct my_item like any_sequence_item is {
        addr: byte;
        data: uint(bits:32);
        rd_wr: bit;
    };

    type seq_type : enum { READ, WRITE };

    sequence my_seq using item: item = my_item, created_driver = my_bfm_u;

    extend my_seq {
        !sequence_type: seq_type;
    };

    extend my_seq is {
        keep soft item.rd_wr == (sequence_type == WRITE) ? 1 : 0;
        clk is @my_driver.clk;

        body() @clk is {
            var rand_num: uint(bits:4);
            var last_addr: byte;

            for i from 0 to 10 {
                grab(my_driver);

                do WRITE my_seq keeping { last_addr == it.addr; };
                wait[rand_num] * clk;

                do READ my_seq keeping { it.addr == last_addr; };

                ungrab(my_driver);

                gen rand_num;
                wait[rand_num] * clk;
            };
        };
    };

    unit my_bfm_u is {
        smp: smp_u;
        clk is @smp.clk;

        run() @clk is also {
            drive_read_write();
        };

        drive_read_write() @clk is {
            item: my_item;

            while (TRUE) {
                item = my_seq.get_next_item();
                smp.addr = item.addr;
                smp.rd_wr = item.rd_wr;
                smp.data = item.data;
                emit my_seq.item_done;
            };
        };
    };

    unit my_agent_u is {
        smp: smp_u is instance;
        bfm: my_bfm_u is instance;
        keep bfm.smp == smp;

        monitor: monitor_u is instance;
        keep monitor.smp == smp;
    };

Formal Verification IVA method.

AP202411193629 — Tue, 01 Apr 2025 20:48:20 GMT

I have gone through the Formal fundamentals with jasper 2403 course and doing the labs. got stuck in the lab 5.changed the tcl to abstract the init_value in if{iva}.and simulated it properly. I am getting cex.thats fine.but i am unable to find the cex lenth using commands.kindly help.

How to Become a Certified Fraud Examiner (CFE) with Comprehensive Study Materials

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UCIe and other specs

masamasa — Tue, 29 Aug 2023 23:12:06 GMT

Hello

What is the difference between UCIe and other specs such as BoW (Bunch of Wires) and OpenHBI?

VoltusFi temperature settings

dakuang01 — Sun, 23 Jul 2023 22:59:46 GMT

Hi,

I ran two same EMIR jobs with transient simulation at different temperatures 27C and 105C. However, 105C one shows less current values for all pwr/gnd than 27C for some reason, which is reversed.

I checked the temp was setting correctly for each runs in the log files but tnom was the same as 27C

Is there anything else I need to check in the setup that might have affected to the current values?

Thanks,

Jane

UCIe: Enabling the Chiplet-based Ecosystem

JHarshit — Wed, 11 Jan 2023 10:59:56 GMT

Universal Chiplet Interconnect Express (UCIe) is a novel specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.

What is a chiplet?

A chiplet is a tiny integrated circuit (IC) with well-defined specific functionality. One can relate this to LEGO building blocks for creating large structures.

Why do we need a Chiplet-based design?

Modern designs on one hand require high-performance computation feasible through lower nanometers (5-7nm), still most part of the design gives better performance with older nodes(16-28nm)

The Chiplet-based design approach opens opportunities to combine chiplets from different process nodes into the same package. This even results in cost reductions of specialized chips.

Possible combinations of disaggregated Chiplets

Need for UCIe?

UCIe provides a common chiplet interconnect that enables the construction of large SOCs that exceed the maximum reticle size. UCIe also allows intermixing of different components from different silicon vendors within the same package and improves the manufacturing yields by using smaller dies.

UCIe will become the generic protocol for On-Chip data transmission as its architecture includes a common Physical layer for multiple protocols. The most significant advantage is that you can change the Physical layer or the upper layers without interfering with either of them. This is due to well-defined interfaces between the different layers, for easier integration with other protocols.

The UCIe specification defines three layers: Physical, Die-to-Die(D2D) Adapter, and Protocol layer. The Physical layer supports multiple lanes with varying speeds, and the Protocol layer is implementation specific, and it can consist of a CXL, PCIe, or proprietary Streaming protocols. UCIe leverages these to move data between chiplets. The data transfer between UCIe links is defined in terms of Flow Control Unit(FLIT) or raw data.

UCIe Layers and Components

Main features of UCIe :

High-Speed Interface
Can be used with multiple protocols
Chiplet-based design for higher yields.

Cadence Verification IP for UCIe is available to support the latest UCIe specification, allowing to simulate the different layers for IP, SOC, and system-level design verification. Semiconductor companies can start using it to fully verify their design and achieve functional verification closure on it within no time.

Stay tuned for more …

Can't drive the Slave Active AXI Stream Tready signal

TomasPrudente — Tue, 13 Dec 2022 05:24:12 GMT

In order to test one specific feature of my DUT I need to take control of the Tready signal of my AXI Stream active slave VIP.

Reading the documentation: Stream VIP Reference for UVM SystemVerilog (stream_sv-uvm_reference.pdf)

I found out this register to take control of the Tready called DENALI_STREAM_REG_driveTready:

I am already using another register to configure the VIP called DENALI_STREAM_REG_EnableTracker to take control of the verbosity of the VIP messages, and it's working as expected:

But when I try to configure the DENALI_STREAM_REG_driveTready I have the error: 'DENALI_STREAM_REG_driveTready': undeclared identifier [12.5(IEEE)].

This is how I'm using (or trying to use) the register configuration within my run_phase():

m_axis_egress_active_slave_agent.regInst.writeReg(DENALI_STREAM_REG_EnableTracker, 0); <-- This is working fine

m_axis_egress_active_slave_agent.regInst.writeReg(DENALI_STREAM_REG_driveTready, 2'b10); <-- This is not compiling at all because it doesn't find the DENALI_STREAM_REG_driveTready

Any suggestion will be really appreciated, thanks.

Tomás Prudente

H12-711_V4.0-ENU HCIA-Security V4.0 Exam Dumps

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test flow in the specman for calling start_test()

muku1kr — Thu, 30 Jun 2022 05:50:54 GMT

Hi there,

I am new to the Specman "e" and am trying to understand the test flow in the specman but not able to understand from where the tests are getting called and also how the phases are getting started in the test environment, I could see the phases are getting called/display in the log file though. any help on the test/phase calling in the specman/UVMe would be really helpful.

and also how the sequence(s) are getting triggered?

Regards,

muku_kr

+escchars option meaning

markris — Fri, 17 Jun 2022 13:58:05 GMT

Does someone know the meaning of this option in Spectre --> +escchars ?? Unfortunately I don't find it in the Spectre manual.

Regular expressions for keeping

LorincAntoni — Wed, 23 Mar 2022 14:48:25 GMT

I have registers defined in vr_ad (with reg_def and reg_fld) and I have a macro that makes me possible to make writes to it, even to fields, e.g.:

wr_reg REG1 keeping {.fld1== val1}

I would like to have an expression that I can use inside the {} with which I could write the same value (e.g. 0) to all the fields of the register, something similar as the "for each" in case of a list. The problem is that I cannot use "for each" in this case as it is not a list but a register with several values. Could you please help me what the regular expression that I could use here is, to have all fields the same value?

Jasper Gold - System Verilog Assertion Prove time estimation

Shahidhussain — Tue, 28 Dec 2021 13:32:42 GMT

Hi all!

I am beginner to System Verilog Assertions based formal verification on Jasper Gold. I am very happy have such a fantastic tool for verification with amazing features. I have written some assertion for a design module. I am noticing that Jasper Gold takes plenty of time (in days) to prove some particular assertions. The bound increase speed is too slow. I just have a couple of queries regarding assertion prove time.

1- What are key factors on which assertions prove time depends?

2- Is there any method/tool/command to estimate the prove time before running the assertion? So that we can set the "set_prove_time_limit" in Jasper Gold.

3- Do selection of proof engine has any thing to do with prove time? and how to estimate which engines are best for a particular assertion?

4- I am also noticing that when I run assertions individually then it gets less time but when I run multiple assertions (parallel or sequentially) at a time then its take too long.

Any help from Cadence community with be a great favor.

Thanks

Driving a spectra /spice (analog) schematic from xcelium

pnpras — Thu, 25 Nov 2021 15:16:24 GMT

Hi,

I have a UVM based TB and I want to drive and test an analog schematic on virtuoso from my UVM environmet. Firstly is this possible? How can I export the schematic into my xcelium UVM based environmet?

I have imported the netlist and spectra model files into my uvm testbench, but I am not able to simulate it.

I am new to mixed signal verification and any tips would be really useful.

Thank You

changing error severity of a vip error

anirudh25820 — Mon, 26 Jul 2021 10:44:46 GMT

hi,

I need to change a severity of a VIP message from error to warning/info.can anyonce help me out with this.

the error is pointing out from vip monitor

User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification

Archana P — Mon, 05 Oct 2020 05:18:15 GMT

I have written a set of user-defined assertions to verify a design formally in Incisive Enterprise Verifier. Is it possible to obtain coverage percentage (block coverage etc) for those assertions? I could find coverage percentage for automatic formal analysis done by the tool on the same design. Everything about coverage for automatic formal analysis is in the manual. My doubt is how to find similar coverage data for user-defined assertions?

Simvision debugging techniques

MaheshKumar — Mon, 03 Aug 2020 02:24:24 GMT

Hi All,

I am using simvision(64) 19.03.a001 version.

I would like to more about debugging in simvision.

1) .svcf (data base saving)

Lets say I ran one testcase and saved the Database as TEST1.svcf, which is a passing scenarios.

I ran one more testcase which is TEST2, which is generally failing scenario. I will load this into simvision along with TEST1.svcf.

Now in the waveform, I have two databaes, one is passing one and one more is failing one.

With this feature, will any difference shown by simvision to identify which signal has caused the fail or where is the exact issue by comparing.

a) I just want to understand using .svcf can we compare data base of pass and fail so that easily we can point out the exact issue ?

b) Lets say we have 100 scenarios and it is difficult to have 100 .svcf's always. So, how can be this used in general way to that it can be re checked for 100 scenarios ?

Kindly advice for both a and b

2) .svwf (saving signals)

Hope this is just saving set of signals and it is independent of particular database. This we can use with any database. Please confirm

Thank You,

Mahesh

MSI-X initialization using denali PCIE vip

jaswanth2397 — Tue, 21 Jul 2020 12:29:21 GMT

Hi,

I am using cadence denali pcie vip to verify my Endpoint device.

EP DUT had MSI-X size for 32 entries during initial write to table ram from RC vip it initializes only 11 out of 32.

I have a debug statement from denali.his file :

uvm_test_top.pcieSve0.ARcPEpEnv0.activeRc(p_0.cfg_0_0) 119044412 ps Debug: MSIX (req:32 allocated:11)

Please tell me why is this happening, What must be done to initialize total entries.

Thanks for the reply,

Jaswanth.

Denali Pcie VIP

jaswanth2397 — Tue, 21 Jul 2020 12:12:56 GMT

Hi,

I am using denali vip for pcie to verify my pcie EP DUT .

I am confused to have two SOMA files, When we have endpoint as DUT does it required to have RC soma file. If yes please someone tell me why we need to configure RC. Is it enough to just configure EP.

Thanks,

Jaswanth

can we get CHI UVC with 4 RN's

swathiv — Thu, 14 May 2020 11:50:52 GMT

Hi Team,

Is CHI Sandbox available with 4 RN's ?

Thanks,

Swathi

Can we configure Chi UVC as CMN

swathiv — Mon, 04 May 2020 07:09:25 GMT

Hi Team,

how to configure CHI VIP to configure for the following configuration

4 RN-F Nodes

1 Home Node

Thanks,

Swathi

How to Control the byte enable for Non-snoopable transaction in CHI UVC

swathiv — Mon, 04 May 2020 06:53:29 GMT

Hi Team,

Though am doing a 8byte write from the sequence , its not writing 8 bytes

kindly Advice.

Note:

Taken reference code from CHI_VIP_Test_Writing doc

Thanks,

Swathi

xmvhdl_p: *F,DLUNNE: Can't find STANDARD at /tools/cadence/installs/XCELIUM1803/tools/inca/files/STD. error while compiling a VHD file

Sarath Krishnan — Thu, 09 Apr 2020 14:23:43 GMT

Hi Team,

I am getting the following error while executing a vhd file using XCELIUM1803. Could you please help me to resolve it ?

srcs/sample.vhd:
xmvhdl_p: *F,DLUNNE: Can't find STANDARD at /tools/cadence/installs/XCELIUM1803/tools/inca/files/STD.
xrun: *E,VHLERR: Error during parsing VHDL file (status 2), exiting.

Thanks

Sarath

I have a question about UVM_INFO in my output log file

kkurenkov — Mon, 27 Jan 2020 14:40:55 GMT

It's seems strange UVM_INFO like that.

UVM_INFO [config_direct_seq.sv(55) (55) (81) (81) (55) (55) (55) (55) (81) (81) (55) (55) (81) ] { 35596.0ns } [mem_sys_st_config_direct_seq_1] [mem_sys_st_config_direct_seq_1] 'mem_sys_st_config_direct_seq_1' is completed
UVM_INFO [config_direct_seq.sv(55) (55) (81) (81) (55) (55) (55) (55) (81) (81) (55) (55) (81) (55) ] { 35596.0ns } [mem_sys_st_config_direct_seq_1] [mem_sys_st_config_direct_seq_1] 'mem_sys_st_config_direct_seq_1' is started
ld end in hvt_mem_sys_tb_top.dut.multi_rw_unit_inst.adm_control[0] at 49666.9ns
UVM_INFO [ys_item_transform.sv(638) (638) (355) (355) (348) (348) (348) (638) (638) (355) (355) (348) (348) (355) (348) ] { 50536.0ns } [xi4_to_memsys_item_transform_0] [UPD] hvt_mem_sys_ld_config_desc is updated
UVM_INFO [config_direct_seq.sv(54) (54) (80) (80) (54) (54) (80) (54) (54) (54) (80) (80) (54) (54) (80) ] { 50536.0ns } [mem_sys_ld_config_direct_seq_0] [mem_sys_ld_config_direct_seq_0] 'mem_sys_ld_config_direct_seq_0' is completed
UVM_INFO [config_direct_seq.sv(54) (54) (80) (80) (54) (54) (80) (54) (54) (54) (80) (80) (54) (54) (80) (54) ] { 50536.0ns } [mem_sys_ld_config_direct_seq_0] [mem_sys_ld_config_direct_seq_0] 'mem_sys_ld_config_direct_seq_0' is started
st end in hvt_mem_sys_tb_top.dut.multi_rw_unit_inst.adm_control[1] at 57652.5ns
UVM_INFO [ys_item_transform.sv(638) (638) (355) (355) (348) (348) (348) (638) (638) (355) (355) (348) (348) (355) (348) (355) ] { 58425.0ns } [xi4_to_memsys_item_transform_1] [CONFIG STORE] [STORE] in uvm_test_top.env.mem_sys_axi4_to_memsys_item_transform_1
UVM_INFO [config_direct_seq.sv(55) (55) (81) (81) (55) (55) (55) (55) (81) (81) (55) (55) (81) (55) (81) ] { 58425.0ns } [mem_sys_st_config_direct_seq_1] [mem_sys_st_config_direct_seq_1] 'mem_sys_st_config_direct_seq_1' is completed

UVM_INFO [config_direct_seq.sv(54) (54) (80) (80) (54) (54) (80) (54) (54) (54) (80) (80) (54) (54) (80) (54) ] { 50536.0ns } [mem_sys_ld_config_direct_seq_0] [mem_sys_ld_config_direct_seq_0] 'mem_sys_ld_config_direct_seq_0' is started

I use AXI VIP and XCELIUM1909

Do you know how to fix this bug?