Allegro X APD - Recent Threads

Why do symmetrical etch layers show different impedance values in Display > Parasitic?

Electro Node — Wed, 10 Jun 2026 11:30:56 GMT

Hi everyone,

I routed clines on L4 and L5 with the same width, and both layers are symmetrical to the shield ground.

However, in Display > Parasitic, I’m seeing different impedance values. I expected them to be similar.

Has anyone seen this before?
Which stackup or cross-section setting should I check first? Could this be related to conductor properties in the field solver?

Thanks in advance!

RE: Why do symmetrical etch layers show different impedance values in Display > Parasitic?

BR202606212147 — Mon, 22 Jun 2026 03:51:50 GMT

Have you checked whether copper roughness, etch factors, or layer-specific conductor properties differ between L4 and L5 in the field solver setup? Those settings can sometimes create unexpected impedance variations even in an apparently symmetrical structure.

How to import a die component from DEF?

SaiPavanl — Mon, 15 Jun 2026 07:09:14 GMT

Cadence IC Package design tools support many formats for importing a die component for placement into your package substrate layout. For standard die components, this includes the Cadence OpenAccess format, industry-standard LEF/DEF, die text files, and D.I.E. format files. For co-design dies, this includes OpenAccess, LEF/DEF, and die abstract files.

While the die text file remains the most common method for importing a die into APD or SiP, LEF/DEF is a good alternative if you need to be able to generate DEF files back out of the package design for sending back to your IC designers if they do not support reading a die text file.

Note: The LEF/DEF flow requires that you have access to the LEF library information for the top-level I/O driver and cover bump macro cells. If you do not have all this information, you will not be able to import a die from DEF, as the DEF file contains only macro-placement data and not the information about the macros themselves. You do not need the LEF information for core cells.

We will discuss importing IC LEF library files for use with your package tools, importing a die design from a DEF file to create a standard die component, and updating your library files when you receive new versions from your IC design team or move to a new release of APD / SiP.

Procedure 1: Readying LEF Library Information for Use with Allegro X APD

Before you can import any DEF file to add it as a die in your package substrate, you must import the corresponding LEF library files.

Because APD and SiP only need the top metal cells like the cover bump and I/O driver macros (those cells containing pins that represent package-accessible die pads in the manufactured die part), these tools generate smaller files containing just the information relevant in the package. These files have a .cml file extension, which stands for Compressed Macro Library.

The Setup > LEF Libraries ("lef lib") command is used to specify a set of related LEF library files and to generate the corresponding CML files for each LEF file. Run this command, which brings up the interface as shown below.

First, specify the name and location of the Library Definition File (LDF). Typically, this will be located in the same directory as your LEF library files. If your LEF library files are stored in a central, shared location, consider creating the LDF file in that directory so that the same file can be accessed by all your designers.

Next, define a library name. Once your LDF file name is specified, the Add button for the library will be activated. Click this button and specify the name. The LDF file can contain multiple sets of LEF files, each one representing a different library of LEF files. In this flow, you will define a single library only. Repeat these steps to define additional libraries if you need to.

With the LDF and library specified, it is time to add all the LEF files that are needed for this type of design. The set of LEF files must include the IC technology information in the first LEF file in the list, followed by all the LEF files which define all the macro cell definitions which contain die pads. Add these files one at a time to the list using the Add button. The technology LEF file will automatically be moved to the top of the list when it is added, but it is up to you to order the remaining LEF files to match the order in which they are referenced in the IC design space.

Once you have finished adding and ordering the LEF files for your library, click on the first LEF file in the list and notice that the status of the CML file is listed as "Does not exist", as shown in the previous image. You need to configure the LEF files to guide the system as to which macro pins represent die pads. This process is not as complicated as it sounds, and is mostly a matter of confirming settings.

Begin by selecting the LEF technology file, the first file in the list ("aio.lef" in this example) and click the Options button. This opens the form shown below, initially on the General page. Here, you need to identify the IC metal layer on which the die pads are located. Normally, this will be the highest metal layer in the technology information. Select the correct layer in the IC Layers grid and set the mapping to "die pin". Then, close this form by clicking OK and, on the main LEF Library form, click the Auto create button. This will generate a CML file for this LEF file; you will notice that the CML status changes to "Up to date" to reflect this.

Note: CML files are located in the same directory as the LEF file to which they belong. Therefore, you MUST have write access to this directory.

Next, for each remaining LEF file, select the file and click the Options button. On the Pins page, set the minimum die pin width and height fields (You may need to obtain these settings from your IC design team if you do not know what the correct values should be).

When you set the values, the list of pin names that will be considered as die pads automatically populates. If you see a pin name that you know should be globally excluded, change its setting in the grid at the bottom of the form. These fields are highlighted in the image below.

When you are happy with the settings, click OK, return to the main LEF Library command form, and again click the Auto create button. Repeat the process for all remaining LEF files.

Note: In the rare case where you have die pads that are smaller than the minimum die pin size filter (or internal connection points that are larger than the filter size), you can use the Macros tab of the Options form to manually adjust the pad type for these pins on the affected macro(s). These customizations will be recorded in the CML file; so, you will not need to enter them again for this file even when you receive a new version of the LEF library.

Procedure 2: Importing a Die Component from DEF

Once your IC library files have been imported and your CML files generated, importing a specific IC design to place a die component instance is very straightforward. Before beginning, ensure that your package substrate cross-section has been set up.

If your DEF file represents a wire bond die, be sure to add a DIESTACK type layer above the top substrate layer or below the bottom substrate layer, depending on which side of the package substrate the die will be mounted to.

With your cross-section defined, run the Add > Standard Die > DEF (Die Pins Only) ("def in") command. You will be presented with the main DEF Import form as shown below.

To import the design from DEF, first ensure that the correct IC library is active. This is shown at the top of the form. If the wrong library is active, change to the proper one using the Library Manager button to the right of the library name. Then, browse to the DEF file that contains your IC design.

Finally, configure the die type and placement information on the bottom portion of the form. Select the correct chip attachment type and orientation (typically, Wire bond Chip-up or Flip chip Chip-down for mounting on top of the package substrate). If this die will go through an optical shrink during fabrication, ensure you set the shrink and scribe values, as appropriate.

The pad layer and the X/Y location of the die origin are also set on this form. However, you can always move the die after initial creation, if you need to, by using the Edit > Move ("move") or Edit > Die Stack ("diestack editor") command. So, do not worry if you do not know the exact placement details or need to optimize the die positioning to optimize the routing on your package substrate.

Click the Import button when you are satisfied with all the information on the form. The die will be imported into the active drawing. You should verify the results to ensure that all your library settings are correct and that no die pads have been missed (and no internal IC pins have been incorrectly flagged as die pads).

Procedure 3: Updating Library Files when They Change or You Update to a New Version of Your Package Design Tool

When you receive new versions of LEF library files from your IC design team, you must refresh the CML files for those LEF files. Do this by running the Setup > LEF Libraries ("lef lib") tool. Browse to your library definition file if it is not already active, and select the library containing the LEF files to be refreshed.

For each LEF file which has been modified, the CML status will show "Out of date" as shown in the image below. Click the Auto create button to regenerate the CML file based on the new LEF file’s contents.

Since the CML file stores your settings from the Options page as well as the macro cell definitions, it is not necessary to open the Options tab prior to performing the update. Any customizations you have made will be preserved when the macros are processed and the new CML generated.

When you move to a newer release of your Cadence IC Package layout design tools, you should perform the same procedures listed above. This time, however, be sure to regenerate ALL CML files. The tool will not automatically refresh your CML files in order to ensure that. If you have multiple releases of APD / SiP installed, the files are not made incompatible with earlier releases of the tools that you are still using.

RE: Why do symmetrical etch layers show different impedance values in Display > Parasitic?

TechnoBobby — Mon, 15 Jun 2026 04:50:38 GMT

Hi Electro Node ,

This is usually caused by an incorrect conductor dielectric constant setting. If it differs significantly from the surrounding dielectric, the field solver may report different impedance values even for symmetrical layers.

Update it in Setup > Cross-section so it matches (or is close to) the surrounding dielectric value.

Hope this helps!

RE: Autorouter Help in APD 24.1

SaiPavanl — Fri, 05 Jun 2026 13:41:44 GMT

Hello, did you try the Auto Bonding Option in APD?

Steps to Run this.

1. Run wirebond select command.

2. Select the Pins

3. Run pop wirebond auto bond in the command window

Autorouter Help in APD 24.1

EA202605267819 — Tue, 02 Jun 2026 13:37:21 GMT

Hello,

I wanted to ask how someone could auto route or begin the process of auto bonding (I don't know if auto bonding is the same as a traditional auto route) a common bond pad line on some y axis to alternating bond fingers using a single auto bonding command. I just recently learned about the auto bonding command after trying to add guide - lines to the top and bottom bond finger lines and wanted to see if I could speed the process up.

My goal is to be able to auto route these large numbers of pads in a short amount of time and not do them individually as well, so as to avoid any error on my part where they might be on the wrong layer so the simulations are all messed up. The layout is roughly as so:

Top Finger - Empty space - Top Finger - Empty space - ...

Empty space - Bottom Finger - Empty space - Bottom Finger - ...

Pad - Pad - Pad - Pad - ....

Where the connects are perfectly orthogonal to the pads and the finger it goes on, all while the pattern between top row and bottom row of fingers is alternating.

Given this information, how would I implement the auto routing function for this?

I tried to write a Python Script to do this for me since the wiring is simple, but unfortunately, I was completely stuck with some issues in the software. If I take a completed wiring and export it, then try to import it back into the project, I'm left with nothing but errors which include:

- A shift of every net 25 microns to the right.

-Some nets that don't appear due to objects not being found for them to lay on. The coordinates of those nets are given, which should be the ones at the very left (negative edge), but they don't appear on the POSITIVE edge. So, it feels like all consistency is gone.

I tried to account for these in the program, but nothing ended up working. The 3 far right nets still don't exist despite giving me an error for them on the left side and the nets are still shifted 25 microns to the right of where I want them to be. Has someone created a python script for this that I could run? Or knows what the issue is?

Thank you.

How to find out a misaligned via from a via stack

SaiPavanl — Fri, 24 Apr 2026 08:54:53 GMT

I am performing a package design with many blind / buried vias. The blind / buried vias of adjacent layers are stacked only if via centers are aligned. Is there a way to find out the misaligned vias?

The via, 1:3, shown in the following image is misaligned from the stack:

Vias can be stacked only if their centers are aligned (as shown below)

You can detect a misaligned via from the Reports > Stacked Via Report command.

Search for the word “misaligned” in the Stacked Via Report to check for the misaligned vias.

If search returns '"misaligned" not found', as shown in the following screenshot, it means that there are no misaligned vias in the design:

If there are any misaligned vias, the report will highlight the misaligned vias as shown below:

You can align these vias to the stack and when you run the report again, it will show '"misaligned" not found'.

RE: How to find out a misaligned via from a via stack

AA202605191046 — Fri, 22 May 2026 07:07:35 GMT

To find misaligned vias in your package design, use the Reports > Stacked Via Report command. Search for "misaligned" in the report; if it's found, the report will highlight the misaligned vias, which you can then align to ensure proper stacking.

How to generate IC style via cut arrays in GDS output?

SaiPavanl — Thu, 21 May 2026 17:34:42 GMT

As designs get more involved in WLP designs, there is a need to create IC style via cut arrays in Packaging tools.

I have created IC style via cut arrays in Allegro X Advanced Package Designer. How do I create a GDSII file from it?

For example, take the following cross-section:

RDL1 (conductor)

VIA1 (dielectric)

RDL2 (conductor)

Assume IC style via cut padstack(s) are correctly created (See the related article). You can now create a streamout file. You need to have a layer mapping file (.cnv) with the following entries:

##########################

72 10 CONDUCTOR RDL1

72 10 VIA_CLASS RDL1

##########################

4 1 VIA_CLASS VIA1

4 1 VIA_CONN VIA1!RDL2

##########################

72 20 CONDUCTOR RDL2

72 20 VIA_CLASS RDL2

###############################

Then, you can have the IC style via cut arrays in GDS.

Here are the steps to export GDS file from APD/SiP:

Manufacture > Stream Out

Provide GDS file name in the Output file name field.
Provide top cell name in the Top structure name field.
Browser the cnv file (which has the correct format mentioned above) for Layer conversion file.
Click on the Export button.

Then, you will have GDS with IC style via cut array as shown in the following image:

RE: How to find out a misaligned via from a via stack

SaiPavanl — Thu, 21 May 2026 11:41:25 GMT

I agree with that

RE: How to find out a misaligned via from a via stack

JV202605125312 — Wed, 13 May 2026 04:07:41 GMT

Blind and buried vias only stack correctly when their centers are perfectly aligned; otherwise, misalignment can cause manufacturing issues, signal integrity problems, and reliability concerns.

[URL=https://treeshateyou.io][color=#FFFFFF][size=1]Trees Hate You[/size][/color][/URL]

RE: How to find out a misaligned via from a via stack

JV202605125312 — Wed, 13 May 2026 04:06:49 GMT

Blind and buried vias only stack correctly when their centers are perfectly aligned; otherwise, misalignment can cause manufacturing issues, signal integrity problems, and reliability concerns.

RE: Connecting to APD from external process to execute skill code

SV202603065248 — Tue, 21 Apr 2026 22:34:50 GMT

Thanks for the response. Here's the setup in more detail:

* Environment: Windows only, single user, single APD session per machine. APD is running interactively with a design already open — I need to attach to that live session, not spawn a headless / -nograph batch APD. (I'm aware of the -s script.il / batch route; it doesn't fit this use case)

* Custom application running as a separate process: We have an in-house desktop tool written in C++ (with some Python) that the user runs on the same machine as APD.

The user clicks a button in our tool → that needs to trigger SKILL execution inside the already-running APD session → we need the return value back in our tool.

* SKILL calls can be Short one-line expressions, e.g. (axlDBGetDesign), or pre-registered SKILL function with arguments. In both three cases we need the return value passed back to the external process (not fire-and-forget).

What I've looked at: Cadence documentation and several forum threads — MPS looks like the right primitive, but I can't find a worked end-to-end example of a Windows C++ (or Python) client exchanging messages with a running APD session, including how the APD-side listener is set up and how responses are returned.

ipcBeginProcess — this seems to go the other direction (APD spawns a child), so I don't think it fits.

What would unblock me: A minimal working example of MPS between an external Windows process and a live APD session (both the SKILL side and the external-client side), or

Confirmation that MPS is the right mechanism for this pattern and pointers to the authoritative reference, or

If MPS isn't the recommended path for my use-case on Windows, feel free to point me to the mechanism Cadence recommends for this.

Connecting to APD from external process to execute skill code

SV202603065248 — Wed, 15 Apr 2026 05:09:11 GMT

Im looking for a way to connect to an existing/active APD session from an external process and executing skill within that APD session. The idea is to create this communication link between our custom workflow tool and APD to streamline execution. The forums point to using MPS (message passing system) but there isn't much documentation on this. Could you pls point me in the right direction.. Im looking for documentation or code samples.

RE: Connecting to APD from external process to execute skill code

JuanCR — Thu, 16 Apr 2026 21:54:26 GMT

Can you describe a bit more about how you are planning to connect or what your setup is?

How to import large pin count devices to Allegro X APD?

SaiPavanl — Fri, 27 Mar 2026 14:52:57 GMT

Allegro X Advacned Package Designer offers an extremely rich environment for supporting and manipulating data from text files, GDSII, some 3rd part EDA vendors and Microsoft Excel spreadsheets in xml format.

Today’s digital design complexity continues to escalate in terms of size, high-speed interfaces, technology pitch, constraints, routing, and bump and ball pin counts.

It is quite common, particularly in the GPU, FPGA, and desktop/server processor market, to see dies with 15k or more bumps. Also, a new trend that is growing quite quickly is both 3D and 2.5D interposers, which can easily grow to 50K bumps or even more, depending on the ASIC, memory, and other glue logic required to make it a system.

These large numbers of pins put pressure on CPU cost, memory, and the layout tool when reading the data and concurrently running the DRC engine.

Importing Device Pins

You can use BGA Text-In, Die Text-In, DIE format, DEF, and GDSII to import pin data. However, the most common format has been the use of Die/BGA Text-In.

Using the spreadsheet import format, you have a new and more efficient process with an overall performance improvement for loading large pin-count device data.

The following Die/Interposer parameters provide processing time metrics for both Die Text-In and Spreadsheet Import for the following design;

The Die/Interposer example above has over 44000 pins and signals. For this application note, we will use the Die/Interposer based XML spreadsheet option vs. the typical Die Text-In process.

A small section of this large Die is shown below that depicts partial die spreadsheet XML information from the excel spreadsheet below (too large to display the entire view since there are 44000 plus cells!.

Additionally, will also include additional settings on how to process BGA/package carrier data using a slightly different option than that of the Die/Interposer method.

The steps below can be used as the generic process for importing large pin count devices via Excel spreadsheet information into Allegro X APD. These will apply to DIE, Interposer and BGA/package carriers.

1. Set Allegro X APD Layout to Symbol Editor Application mode and go to Setup > Application > Symbol Edit…

2. In Canvas, RMB > Add Component. For your Die/Interposer xml data, define the information on the Options form for your type of component to be created and all the related information.

3. Enter all associated parameters for your Die/Interposer

4. Alternatively, for your BGA/package carrier xml data, define the information on the Options form for your type of component to be created and all the related information.

Select Create Component at the bottom of the Options form

6. Set Find Filter to Symbols.

7. Select Edit > Properties

8. Select your Symbol

9. In Edit Property Form, Select NODRC_SYM_SAME_PIN

Note; The NODRC_SYM_SAME_PIN property needs to be set to command the online DRC engine not to check same pins defined within the symbol instance. Imagine the DRC engine doing a spacing check on 44,000 or more pins and variable pitches!

There is no other way to add the NODRC_SYM_SAME_PIN property before a symbol is created and thus controlling the import processing performance of these large pin count devices.

10. Select Apply then OK

Note: This CANNOT be done using the die or BGA text in editor or any other import data option in SiP Layout.

11. Set Find filter to Comps or Symbols, right-click, and then choose Add pin.

12. Set Find filter to Comps or Symbols, right-click, and then choose Pin pitch settings.

13. Optionally, Set Find filter to Comps or Symbols, right-click, and choose Pin numbering settings

14. In the Option pane, set parameters for Pin configuration. Ensure you either select the correct pad stack or create a new one as required.

15. Select Pattern definition and select Spreadsheet from the Pattern style list.

16. In File name, specify the XML file and configure the rest of the fields.Spreadsheet bump/ball array is attached to the cursor.

17. Place ball/bump array within boundary of component definition

Degassing with APD+

PCBTech — Wed, 24 Aug 2022 15:48:57 GMT

Degassing, also called outgassing, is a common feature in IC package designs. Degassing is a process where you perforate power planes, voltage planes, and filled shapes in your design. Degassing holes let the gas escape from beneath the metal during manufacturing of the substrate.

Reasons to go for degassing:

Prevents forming of gas bubbles under the metal (Otherwise, it would cause the surface of the metal to become uneven.)
Lowers the density of metal in a region or across an entire layer of your design
Improves the vacuum-lamination and pattern-plating manufacturing processes

The degassing feature in Allegro Package Designer Plus is an automated process where you can specify the details of the perforation array pattern. This generates the exact placement of voids across the entire shape. The tool does not create a void in the pattern if, in doing so, it violates any of the spacing or manufacturing requirements for degassing.

Users can also set layer-based parameters for degassing. This feature has the ability to define degassing per layer. It provides a quick way to set up layer-based degassing parameters both at the hierarchical level and individual level.

Allegro Package Designer Plus with the Silicon Layout option provides the Advanced Shape Degassing command in the Si Layout menu. This command uses the new data model. It provides significant memory and file size reduction, and speeds up overall performance.

You can also use the Off-Grid Degassing Holes command to add holes for metal areas where regular degassing pattern and matrix-based holes cannot be added due to conflicts with the routing, teardrops, vias, small metal areas, and shape edges.

Team PCBTech

Cadence Design Systems

RE: Degassing with APD+

FA20260303562 — Wed, 04 Mar 2026 03:00:45 GMT

I totally get the struggle with degassing in APD+. Have you considered pairing it with a real-time monitoring approach? It could provide insights into optimal parameters and help avoid those dreaded bubbles during lamination. Just a thought!

RE: Electrical Net Classes Import Using technology file (.dcfx, .tcfx)

AnanthVedalaLM — Tue, 03 Mar 2026 18:45:10 GMT

Yes, i have checked the ElectricalCset check box while exporting, i was facing the issue for a different reason and the issue got resolved.

Electrical Net Classes Import Using technology file (.dcfx, .tcfx)

AnanthVedalaLM — Tue, 24 Feb 2026 20:57:17 GMT

I'm trying to import The net classes in APD from a technology file with extension (.dcfx and also tried with .tcfx) The spacing and Physical Netclasses are being imported but not Electrical Net Classes, is there any default setting that we need to change in the APD Constraints Manager or is there any other issue

RE: Electrical Net Classes Import Using technology file (.dcfx, .tcfx)

Master Shifu — Tue, 03 Mar 2026 09:18:50 GMT

Did you check while exporting the technology/constraints , the contents has Electrical constraints selected ? technology file will import just the netclass definitions, if you import the constraints the nets will also be populated if the netname matches the destination design.

FAQ about Net resistance in APD+ and Allegro

JuanCR — Mon, 26 Jan 2026 19:01:49 GMT

Here are some frequently asked questions regarding Net Resistance in Allegro PCB Editor and Advanced Package Designer:

What does the net resistance include?

Net resistance includes traces, shapes, and ratsnest only. For the complete net with vias and other objects, you need to use SIGRITY tools for elaborate power analysis.

What thickness is used to calculate traces, ratsnest, and shapes?

The thickness of the layer where they are routed will be used for traces and shapes. For ratsnest, parameters defined in "Unrouted Interconnect Models" will be used.

What trace width is used in the calculation? Does this come from the cross section or from the width that is actually in the design?

The actual width of the trace will be used.

What is the conductivity or resistivity that is used? Is it the conductivity of the material for a given layer?

Yes, it is the material's conductivity for a given layer in the cross-section.

What other questions do you have about this topic? Leave them in the comments below.

While opening *.mcm file in APD 2023

AM202601203416 — Wed, 21 Jan 2026 09:33:14 GMT

While opening files in APD, getting error SPMHOD-29.. which read unable to open design. design compatibility log says "This design was last saved with: apd 24.1 P001 - 9/4/2024".. How fixed this issues.

RE: While opening *.mcm file in APD 2023

Elecguy — Fri, 23 Jan 2026 00:18:38 GMT

what version and hotfix are you trying to open the design with?

How to create soldermask at pins in APD+ and set up soldermask-to-soldermask spacing DRC

SaiPavanl — Fri, 16 Jan 2026 17:17:52 GMT

When I try to create a soldermask for pins of BGA or DIE pad using the Create Bond Finger Soldermask command, I cannot choose the Pins object in Find Filter. I can choose only Finger and Vias.

How can I create soldermask at pins in APD, and how can I set the DRC for the soldermask-to-soldermask spacing for the pin?

Follow the steps given below to create soldermask at pins in APD:

1. Open Allegro Package Designer+ and go to Setup > User Preferences

2.Enable the icp_soldermask_allow_pins variable by going to Ic_packaging > Early_adopter.

3.To create soldermask for pins, go to Manufacture > Create Bond Finger Soldermask.

4. Choose Pins in the Find Filter window.

5.Select the pins to create soldermask. To have an option for checking soldermask spacing, change Class/Subclass in the Options pane from Substrate Geometry – Soldermask_Top/Bottom to Component Geometry – Soldermask_Top/Bottom.

Follow the steps given below to set up Soldermask-to-Soldermask spacing:

1. Go to Setup > Constraints > Modes

2. In the Design tab under the Soldermask section, set the Soldermask to soldermask DRC value and enable the DRC.

3.Check the SOLDERMASK_SPACING DRC created in the layout.