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<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Allegro X Capture CIS - Recent Threads</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>Browsable CIS link always opens in Microsoft Edge</title><link>https://community.cadence.com/thread/66217?ContentTypeID=0</link><pubDate>Wed, 29 Jul 2026 15:41:12 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f0d44af6-5292-4f03-8eb4-ac6364d5b8cb</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66217?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66217/browsable-cis-link-always-opens-in-microsoft-edge/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;Hi all,&lt;br /&gt;&lt;br /&gt;I am using Capture CIS and have configured a property as Browsable, allowing users to click a link directly from CIS Explorer and open the associated document or webpage.&lt;br /&gt;The functionality works as expected, but whenever I click the link, it always opens in Microsoft Edge. On my system, I would prefer these links to open in Google Chrome instead.&lt;/p&gt;
&lt;p&gt;I checked the CIS configuration but could not find any setting that allows me to specify which browser should be used for browsable links.&lt;/p&gt;
&lt;p&gt;Is it possible to configure CIS to launch browsable links using a specific browser such as Chrome? &lt;br /&gt;&lt;br /&gt;Thanks!&lt;/p&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>SpaceMousen (3D Mouse) support</title><link>https://community.cadence.com/thread/66198?ContentTypeID=0</link><pubDate>Sat, 25 Jul 2026 23:15:08 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8ccdd827-a434-486c-9185-8ee3918e2c96</guid><dc:creator>JH202606267441</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66198?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66198/spacemousen-3d-mouse-support/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Has it been brought up that support for the 3D Connexion SpaceMouse would be really helpful for panning, rotating, and zooming both 2D and 3D UI. Please add support for using the SpaceMouse.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Leveraging Instance and Occurrence Annotation Modes in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66187?ContentTypeID=0</link><pubDate>Tue, 21 Jul 2026 19:28:40 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1581197c-f58d-40d0-a74a-0b0715c10d2e</guid><dc:creator>TechnoBobby</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66187?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66187/leveraging-instance-and-occurrence-annotation-modes-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;If you&amp;#39;re working with hierarchical designs in OrCAD Capture, you may have noticed both &lt;strong&gt;Instance&lt;/strong&gt; and &lt;strong&gt;Occurrence&lt;/strong&gt; annotation modes in the Annotate window.&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;What is the difference between Instance and Occurrence annotation modes?&lt;br /&gt;&lt;br /&gt;&lt;/strong&gt;The key difference lies in how reference designators are assigned in hierarchical designs.&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;a) Instance Mode&lt;/strong&gt; assigns reference designators at the component instance level and is commonly used for &lt;strong&gt;flat designs&lt;/strong&gt; or &lt;strong&gt;simple hierarchical designs&lt;/strong&gt;.&lt;br /&gt;&lt;strong&gt;b) Occurrence Mode&lt;/strong&gt; assigns reference designators at the occurrence level, allowing each use of a hierarchical block to have &lt;strong&gt;unique reference designators&lt;/strong&gt;.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1784661774380v3.png" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;The recommended annotation mode depends on the design structure. Understanding when to use each mode helps ensure unique reference designators across reused blocks and avoids manual renumbering effort.&lt;br /&gt;&lt;br /&gt;Another useful concept is the relationship between the&amp;nbsp;grey and yellow columns shown in the Property Editor. The grey column represents instance properties, while the yellow columns represent occurrence properties.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:300px;max-width:414px;" height="300" src="https://community.cadence.com/resized-image/__size/828x600/__key/communityserver-discussions-components-files/109/pastedimage1784661969614v4.png" width="414" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;Follow up questions do let us know!!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Is it possible to create inverted pins in the Part Editor?</title><link>https://community.cadence.com/thread/66164?ContentTypeID=0</link><pubDate>Wed, 15 Jul 2026 09:22:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7328848d-0be4-4cd9-af44-dccae3127489</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66164?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66164/is-it-possible-to-create-inverted-pins-in-the-part-editor/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span data-teams="true"&gt;Hi,&lt;br /&gt;&lt;br /&gt; I&amp;rsquo;m creating a new schematic symbol in the OrCAD Capture Part Editor and was wondering if it&amp;rsquo;s possible to define a pin as inverted directly in the Part Editor.&lt;br /&gt;If so, what&amp;rsquo;s the recommended way to create or display inverted pins while creating the symbol?&lt;br /&gt;&lt;br /&gt;Thanks.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>ERROR  (ORCOMMN-12005) Unable to launch Orcad Capture.</title><link>https://community.cadence.com/thread/66152?ContentTypeID=0</link><pubDate>Thu, 09 Jul 2026 12:05:18 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fb050bee-c79c-4c35-83d2-0b5d903fb39d</guid><dc:creator>Shashank</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66152?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66152/error-orcommn-12005-unable-to-launch-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;strong&gt;ERROR&amp;nbsp; (ORCOMMN-12005) Unable to launch Orcad Capture. A valid license wasn found at the 5280@hostname license server. Update the license server configuration to include OrCAD Capture licenses&lt;/strong&gt;&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;I have installed &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-weight="bold" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal"&gt;OrCAD 25.1&lt;/span&gt; and configured the environment variables to point to the license server. Additionally, I have verified that ports &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-weight="bold" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal"&gt;5280&lt;/span&gt; and &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal" data-w-weight="bold"&gt;3000&lt;/span&gt; are in the listening state.&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;However, I am still encountering the attached error.&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;Could you please let me know if I have missed any configuration steps, or advise on how this issue can be resolved?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Conversion of  concept HDL symbol to .olb?</title><link>https://community.cadence.com/thread/66151?ContentTypeID=0</link><pubDate>Thu, 09 Jul 2026 11:11:39 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b7f5844f-cb5b-4874-ad40-1c6ecb3947a8</guid><dc:creator>BM202607094213</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66151?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66151/conversion-of-concept-hdl-symbol-to-olb/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I have symbols in concept HDL format (.prt, .ptf, .css, .tag). How can I convert them to .olb?&lt;/p&gt;
&lt;p&gt;Is there any tool?&lt;/p&gt;
&lt;p&gt;i have tried to convert using Allegro project manager. am getting below attached error.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1783595430915v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;Kindly suggest the procedure.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Balkis&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How does OrCAD Capture decide which net alias is used in the PCB netlist?</title><link>https://community.cadence.com/thread/66132?ContentTypeID=0</link><pubDate>Fri, 03 Jul 2026 20:43:05 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cb4a4f53-253f-4b6d-b767-62a7b3d13f6a</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66132?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66132/how-does-orcad-capture-decide-which-net-alias-is-used-in-the-pcb-netlist/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;br /&gt;&lt;br /&gt;I have a schematic where a single net has multiple net aliases. For example, a power net is labeled as both VCC and +5V at different locations in the design. When creating the netlist for PCB, how does OrCAD Capture determine which net name is transferred to the PCB tool? Is there a way to explicitly control which alias is used in the generated netlist without removing the other net aliases?&lt;br /&gt;&lt;br /&gt;Thanks.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Leveraging Design Review &amp; Markups in OrCAD X Capture CIS 25.1</title><link>https://community.cadence.com/thread/66119?ContentTypeID=0</link><pubDate>Tue, 30 Jun 2026 14:10:41 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d43ac01e-d822-4ed9-8016-e39fa82255b5</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66119?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66119/leveraging-design-review-markups-in-orcad-x-capture-cis-25-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Collaboration plays a critical role in today&amp;rsquo;s schematic design workflows, especially when multiple engineers are working on the same project. Traditional feedback methods&amp;mdash;like emails or screenshots&amp;mdash;can often lead to miscommunication and delays.&lt;/p&gt;
&lt;p&gt;To address this, OrCAD X Capture CIS 25.1 introduces the Design Review and Markup feature, enabling a more streamlined and interactive review process directly within the schematic environment.&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;What is Design Review &amp;amp; Markup?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;The Design Review and Markup feature allows users to:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Add comments directly on the schematic canvas&lt;/li&gt;
&lt;li&gt;Highlight areas using graphical markups (rectangles and arrows)&lt;/li&gt;
&lt;li&gt;Tag team members for collaboration&lt;/li&gt;
&lt;li&gt;Embed review feedback within the design itself&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;This ensures that all stakeholders can view and act on feedback within the same design.&lt;br /&gt; &lt;br /&gt; &lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Add Comments &amp;amp; Markup&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Open your schematic in &lt;strong&gt;OrCAD X Capture CIS&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Go to &lt;strong&gt;Tools &amp;rarr; Markup&lt;/strong&gt; (opens Comments panel)&lt;/li&gt;
&lt;li&gt;Click &lt;strong&gt;New Comment&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Mark the area using:&lt;ul&gt;
&lt;li&gt;Rectangle ➝ highlight region&lt;/li&gt;
&lt;li&gt;Arrow ➝ point to object&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;Enter your comment (use &lt;strong&gt;@username&lt;/strong&gt; to tag users)&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Click &lt;strong&gt;Submit&lt;/strong&gt; &amp;rarr; Comment is saved in design&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Picture1.png" /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Review &amp;amp; Respond to Comments&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Open schematic and go to &lt;strong&gt;Tools &amp;rarr; Markup&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Select a comment &amp;rarr; Auto-zoom to location&lt;/li&gt;
&lt;li&gt;Add replies or update feedback&lt;/li&gt;
&lt;li&gt;Mark as &lt;strong&gt;Resolved&lt;/strong&gt; once addressed&lt;br /&gt;&lt;br /&gt;&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Picture2.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;&lt;img style="max-height:400px;max-width:500px;" alt=" " src="https://community.cadence.com/resized-image/__size/1000x800/__key/communityserver-discussions-components-files/109/Picture3.png" /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;The Design Review and Markup feature in OrCAD X Capture CIS 25.1 brings collaboration directly into the schematic, enabling teams to communicate more efficiently and reduce design iteration cycles.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt; &lt;br /&gt;&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/66098?ContentTypeID=0</link><pubDate>Wed, 24 Jun 2026 16:37:25 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b70eb17f-a06d-4859-babe-7f9e3327b886</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>7</slash:comments><comments>https://community.cadence.com/thread/66098?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I recently encountered an odd software bug while drawing schematics in OrCAD Capture.&lt;/p&gt;
&lt;p&gt;1. Create a blank OrCAD Capture project, and add two schematic pages: Page1 and Page2.&lt;/p&gt;
&lt;p&gt;2. Place two off-page connectors on Page1 with the net names A+9 and A+_ respectively.&lt;/p&gt;
&lt;p&gt;3. Place three off-page connectors on Page2 with the net names A+9, A+_ and A_ respectively.&lt;br /&gt;(The leading letter &amp;quot;A&amp;quot; can be replaced with any alphabetic character.)&lt;/p&gt;
&lt;p&gt;Right-click any off-page connector and select the Signals option to bring up the signal navigation list. You will see disordered, incorrect jump targets in this list. Nevertheless, the exported final netlist contains fully correct electrical connections as expected.&lt;/p&gt;
&lt;p&gt;You can test the jump function by sequentially clicking every off-page connector on both schematic pages to reproduce this defect.&lt;/p&gt;
&lt;p&gt;This makes people mistakenly believe that the signals are not connected when actually checking the wiring relationships in the schematic.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="color:#0000ff;"&gt;&lt;/span&gt;&lt;/p&gt;
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&lt;div&gt;&lt;span style="color:#ff0000;"&gt;Supplemental Note: This issue can only be reproduced after launching PCB Editor or PCB Presto.&lt;/span&gt;&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
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&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Increasing Icon/menu size in capture</title><link>https://community.cadence.com/thread/66096?ContentTypeID=0</link><pubDate>Wed, 24 Jun 2026 07:11:28 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1da79788-a10e-49db-8df8-ea4138503957</guid><dc:creator>Siri</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66096?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66096/increasing-icon-menu-size-in-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;I would like to increase the icon size in OrCAD Capture. Is there a setting available to adjust the icon size?&lt;/p&gt;
&lt;p&gt;Please let me know the steps if this is possible.&lt;/p&gt;
&lt;p&gt;Thanks in advance.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Hierarchical design cut paste causing refdes changes</title><link>https://community.cadence.com/thread/66090?ContentTypeID=0</link><pubDate>Mon, 22 Jun 2026 05:17:45 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9bfa6b3b-90b8-4c1c-829e-2cdbcf14c1b4</guid><dc:creator>BoardIQ</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/66090?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66090/hierarchical-design-cut-paste-causing-refdes-changes/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;We are using Allegro Capture CIS ver 22.1.&lt;/p&gt;
&lt;p&gt;My design is using hierarchical blocks across several pages. When I move a hierarchical block from one page to another by Cut + Paste, the refdes inside the hierarchical block gets changed. This affects our layout of the PCB.&lt;/p&gt;
&lt;p&gt;Strange thing about this is that it affects only few hierarchical blocks, whereas it works fine with some hierarchical blocks.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Does anyone else face a similar problem?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>I am not able to generate pdf in allegro dehdl 24.1</title><link>https://community.cadence.com/thread/66084?ContentTypeID=0</link><pubDate>Thu, 18 Jun 2026 05:52:08 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6061d667-c0fc-4df9-8b92-322ebb79dcea</guid><dc:creator>Shashank</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66084?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66084/i-am-not-able-to-generate-pdf-in-allegro-dehdl-24-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have below licenses,&lt;/p&gt;
&lt;p&gt;Allegro Library Authoring (PCB Librarian)&lt;/p&gt;
&lt;p&gt;Allegro PCB Designer [Schematic]&lt;/p&gt;
&lt;p&gt;I am using&amp;nbsp;&lt;span style="color:#ff6600;"&gt;&lt;span style="color:#000000;"&gt;Allegro PCB Designer [Schematic],&lt;/span&gt;&amp;nbsp;&lt;span style="color:#000000;"&gt;and trying to export pdf by going to&lt;span&gt;&amp;nbsp;&lt;/span&gt;FILE-&amp;gt;PUBLISH PDF&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="color:#000000;"&gt;But i am getting below error,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;ERROR(SPCOCN-152): The license for this feature could not be&lt;br /&gt;checked out because it is temporarily unavailable. Contact&lt;br /&gt;your administrator to check the license server.&lt;/p&gt;
&lt;p&gt;How can i resolve this and generate a pdf.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>OrCAD export Library to xml and importing again results in different symbols</title><link>https://community.cadence.com/thread/66079?ContentTypeID=0</link><pubDate>Wed, 17 Jun 2026 06:14:40 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d8df112a-8952-4ea0-a10b-41ed5de0f527</guid><dc:creator>PatEscher</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66079?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66079/orcad-export-library-to-xml-and-importing-again-results-in-different-symbols/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&amp;nbsp;&lt;br /&gt;I am exporting a library.olb to an xml file and import it again afterwards into a new olb.&lt;br /&gt;The results are different. at the minimum, I am losing all the fonts e.g. on the labels.&lt;/p&gt;
&lt;p&gt;having a look at the created xml, it seems that this information is not output.&lt;/p&gt;
&lt;p&gt;is this a bug in the exporter and importer functionality of&amp;nbsp;XMATIC&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Patrick&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to clear Error (OrCAD-1628)</title><link>https://community.cadence.com/thread/66078?ContentTypeID=0</link><pubDate>Wed, 17 Jun 2026 05:37:01 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:91018751-20cd-4710-8dac-446a1a5dffaf</guid><dc:creator>kabalee</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66078?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66078/how-to-clear-error-orcad-1628/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;HI Team,&lt;/p&gt;
&lt;p&gt;I am using a 6-pin DC-DC converter in my OrCAD CIS design. Pins 4 and 6 are designated as &amp;#39;Power&amp;#39; type pins for the voltage output (Vout). However, I am encountering an error whenever I connect a VCC or +15V rail to these pins&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;span&gt;Error (Orcad-1628) Possible pin type conflict for Vout. How to resolve this issue.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>OrCAD Capture annotation issues for a heterogenous part in a hierarchical design</title><link>https://community.cadence.com/thread/66067?ContentTypeID=0</link><pubDate>Sat, 13 Jun 2026 03:26:16 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7138f46e-0d0d-4646-8714-96ee5bef9967</guid><dc:creator>SF202503203610</dc:creator><slash:comments>7</slash:comments><comments>https://community.cadence.com/thread/66067?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have a hierarchical block that is used 64 times.&amp;nbsp; Within that block I have a quad opamp that was pulled from the included OrCAD library.&amp;nbsp; The reference designators are U?A, U?B, U?C, U?D.&amp;nbsp; When I annotate this block, (Update Selection is selected). I do not get the annotation that I desire.&amp;nbsp; I want&lt;/p&gt;
&lt;p&gt;Instance 1:&amp;nbsp; U1A, U1B, U1C, U1D&lt;/p&gt;
&lt;p&gt;Instance 2:&amp;nbsp; U2A, U2B, U2C, U2D&lt;/p&gt;
&lt;p&gt;....&lt;/p&gt;
&lt;p&gt;Instance 64:&amp;nbsp; U64A, U64B, U64C, U64D&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;but what I am getting is&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Instance 1: U1A, U2B, U2A, U2C&lt;/p&gt;
&lt;p&gt;Instance 2: U1B, U3A, U2D, U3B&lt;/p&gt;
&lt;p&gt;etc&lt;/p&gt;
&lt;p&gt;I have tried using Update Occurrence, Update Instances:, Annotate as per PM Ordering, Annotate as per page ordering in the title blocks, Preserver Designator, and Auto-package Heterogeneous Part Using First Match, and they seem to have no effect.&amp;nbsp; I have tried &amp;quot;Advanced Annotation&amp;quot;&amp;nbsp; but it just opens and locks up.&amp;nbsp; The only button that works is the X to close the window. I even changed the reference designator for this part to UQ?A, UQ?B, UQ?C, UQ?D so that there would be no conflicts with any other &amp;quot;U&amp;quot; parts, and the output was pretty much the same.&amp;nbsp; I have OrCAD X Capture 23.1, but I have noticed this behavior in previous versions of OrCAD.&amp;nbsp;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I&amp;#39;m beginning to think the only solution to this is to annotate it, then go in and manually change all 256 reference designators (4x64).&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Debug the missing Part Number</title><link>https://community.cadence.com/thread/66064?ContentTypeID=0</link><pubDate>Fri, 12 Jun 2026 05:26:34 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b703de1e-8f65-49da-8bd9-74be396abc29</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66064?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66064/debug-the-missing-part-number/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;In OrCAD X Capture CIS, the &lt;em&gt;Part Number&lt;/em&gt; column appears blank in Live BOM and Part Manager for existing components, even though the value exists in the database. The workspace is set to &lt;em&gt;Local&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;What is the most likely root cause?&lt;/strong&gt;&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:190px;max-width:202px;" height="190" src="https://community.cadence.com/resized-image/__size/404x380/__key/communityserver-discussions-components-files/109/pastedimage1781241779252v1.png" width="202" alt=" " /&gt;&amp;nbsp;&amp;nbsp;&lt;img style="max-height:258px;max-width:472px;" height="258" src="https://community.cadence.com/resized-image/__size/944x516/__key/communityserver-discussions-components-files/109/pastedimage1781241791101v2.png" width="472" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1781241799829v3.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;A. The database is not connected properly, so Live BOM cannot fetch any properties for existing parts.&lt;br /&gt; B. In the CIS configuration, the &lt;em&gt;part_number&lt;/em&gt; field is mapped to a different OrCAD property name (for example, &lt;em&gt;PART_NUMBER_NEW&lt;/em&gt;) than the property name used by the existing schematic parts.&lt;br /&gt; C. Live BOM does not support displaying Part Number information when the workspace is set to &lt;em&gt;Local&lt;/em&gt;.&lt;br /&gt; D. The existing parts in the design must be re-placed from the CIS database before Live BOM can display the Part Number field.&lt;br /&gt;&lt;br /&gt;Try the scenario and share observations.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Happy Learning !!&lt;/p&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66059?ContentTypeID=0</link><pubDate>Wed, 10 Jun 2026 13:41:35 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8385581c-5ec8-42d3-b4ef-68ce8d3c5516</guid><dc:creator>Jeet</dc:creator><slash:comments>6</slash:comments><comments>https://community.cadence.com/thread/66059?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Starting with version 25.1, you can save and reuse Design Template settings to maintain consistency across projects. Design Template allows you to define default settings for new schematic designs, including fonts for various schematic objects, title block information, page size, grid references, and more.&lt;/p&gt;
&lt;p&gt;To save and reuse Design Template settings, follow the given steps-&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Navigate to &lt;strong&gt;Options&lt;/strong&gt; &amp;gt; &lt;strong&gt;Design Template&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;Customize the settings as required, including fonts, page size, title block, grid references, and other parameters.&lt;/li&gt;
&lt;li&gt;Once customization is complete, click Save. A dialog box will prompt you to save the configuration as a .dtp file at your preferred location.&lt;/li&gt;
&lt;li&gt;To apply the saved settings later, click Load in the Design Template dialog box and select the saved .dtp file from the desired location.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1781098685237v1.png" /&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This feature allows designers to reuse design properties across new schematic designs, eliminating the need for redundant redefinition. Additionally, it enables seamless sharing of template files among teams and ensures consistent formatting in&amp;nbsp;designs.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Exclude description while update part status</title><link>https://community.cadence.com/thread/66042?ContentTypeID=0</link><pubDate>Wed, 03 Jun 2026 16:54:15 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ef22d1c0-f2a9-4a93-b51f-6f98af3203ba</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66042?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66042/exclude-description-while-update-part-status/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span&gt;In Part Manager, when I run Update Part Status, Capture reports property mismatches between the schematic part and CIS. If I click Yes to update, all mapped properties get updated.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;In my case, I want most properties to stay in sync with CIS, but the Description in the schematic is intentionally different. Once l accept the mismatch dialog, there doesn&amp;#39;t seem to be any way to prevent Description from being updated.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;Is there any option to exclude Description from Update Part Status, or remove it from the mismatch comparison? Or is this simply how Part Manager is designed?&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How to close the preview when print a pdf in orcad 17.4</title><link>https://community.cadence.com/thread/66027?ContentTypeID=0</link><pubDate>Tue, 02 Jun 2026 02:55:59 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:42e7d6aa-5191-4120-affe-27400b2088ef</guid><dc:creator>JW202606018116</dc:creator><slash:comments>5</slash:comments><comments>https://community.cadence.com/thread/66027?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66027/how-to-close-the-preview-when-print-a-pdf-in-orcad-17-4/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;There are some questions wtih my orcad 17.4.&lt;/p&gt;
&lt;p&gt;When I print a pdf(Adobe pdf or microsoft to pdf),it always came a print preview progress.And may cost &lt;span&gt;1minutes&lt;/span&gt; to 2minutes.&lt;/p&gt;
&lt;p&gt;How can I do with it.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Seeing true Values in CIS explorer ,</title><link>https://community.cadence.com/thread/66024?ContentTypeID=0</link><pubDate>Mon, 01 Jun 2026 12:51:54 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:17cf7096-f9a5-423a-883b-b097edee4a39</guid><dc:creator>Mhawley1</dc:creator><slash:comments>5</slash:comments><comments>https://community.cadence.com/thread/66024?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66024/seeing-true-values-in-cis-explorer/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have a problem where in CIS explorer you put in a value a part and it finds parts based on characters and not the real value .&amp;nbsp;&lt;/p&gt;
&lt;p&gt;For example, if I type in 10uF in the value field it finds 10uF capacitors and also 110uF capacitors. Note the Compare field is = not contains . it still behaves the same way .&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Has anyone else witnessed this and got around it ?&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/66015?ContentTypeID=0</link><pubDate>Thu, 28 May 2026 10:52:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:63b48930-1dc9-4d15-88f0-33df42d03fb7</guid><dc:creator>Renu Vibha</dc:creator><slash:comments>35</slash:comments><comments>https://community.cadence.com/thread/66015?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Got questions on OrCAD Capture? Curious about what&amp;rsquo;s new, insights to resolve day to day workflow challenges? This is your chance to get answers&amp;mdash;directly from the expert.&lt;/p&gt;
&lt;p&gt;Join us here (&lt;a href="https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis"&gt;AllegroX Capture&lt;/a&gt; /or &lt;a href="https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl"&gt;Allegro TCL&lt;/a&gt;) , on&amp;nbsp;&lt;strong&gt;June 10, 2026 at 7:30-8:30PM IST &amp;nbsp;&lt;/strong&gt;for a live session, moderated by Cadence Expert, where you can interact, learn, and elevate your design skills.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;What&amp;rsquo;s in it for you?&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Get expert answers to your day-to-day design challenges&lt;/li&gt;
&lt;li&gt;Learn from practical use cases and peer discussions&lt;/li&gt;
&lt;li&gt;Engage in a dynamic session designed for maximum value and insights&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;Key Topics:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Creating &amp;amp; Managing Variants (Part Manager)&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;CIS Explorer&lt;/strong&gt; (Place Database Part, Link Database Part &amp;amp; more)&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;Don&amp;rsquo;t miss this opportunity to connect, learn, and grow with the community.&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Bring your questions&lt;/li&gt;
&lt;li&gt;Share your experiences&lt;/li&gt;
&lt;li&gt;Be part of the energy&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;Let&amp;rsquo;s make this an engaging, insightful, and impactful session together!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Managing Cross-Probe Results Efficiently in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66006?ContentTypeID=0</link><pubDate>Wed, 20 May 2026 20:25:51 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:095f6ad0-668c-4716-8c68-e19045acb706</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66006?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66006/managing-cross-probe-results-efficiently-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;OrCAD X Capture CIS introduces the &lt;strong&gt;XProbe Results&lt;/strong&gt; window to improve cross-probing usability.&lt;/p&gt;
&lt;p&gt;When performing cross-probing between schematic and layout, instead of opening multiple schematic pages, the results are now consolidated into a &lt;strong&gt;dedicated XProbe Results window&lt;/strong&gt;. This allows you to &lt;strong&gt;view, track, and manage all probed objects (components, nets, pins)&lt;/strong&gt; in one place, reducing design clutter.&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Open schematic in &lt;strong&gt;OrCAD X Capture CIS&lt;/strong&gt; and board in &lt;strong&gt;Allegro X PCB Editor&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Ensure designs are synchronized&lt;/li&gt;
&lt;li&gt;Cross-probe any component/net/pin from schematic or layout&lt;/li&gt;
&lt;li&gt;View results in the &lt;strong&gt;XProbe Results window&lt;/strong&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1779308676934v1.png" alt=" " /&gt;&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This makes cross-probing between &lt;strong&gt;Capture CIS and Allegro PCB Editor&lt;/strong&gt; much more efficient and controlled.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Try this and share insights if you find this helpful.&lt;/p&gt;
&lt;p&gt;Happy Learning!!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Increase default pin spacing when creating parts from spreadsheet</title><link>https://community.cadence.com/thread/65992?ContentTypeID=0</link><pubDate>Thu, 07 May 2026 18:53:06 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:454b0c76-4e3b-40e8-be87-ed4703ca696c</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65992?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65992/increase-default-pin-spacing-when-creating-parts-from-spreadsheet/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I&amp;#39;ve been using New Part from&amp;nbsp;spreadsheet in Capture CIS to generate new library symbols, and overall the workflow is working well.&lt;br /&gt;One thing I&amp;#39;m trying to adjust is the default spacing between pins in the&amp;nbsp;generated symbols. Right now the imported parts are created with pins placed fairly close together, and for larger symbols or multi-pin devices the symbols become a little difficult to read during schematic review.&amp;nbsp;Is there a way to increase the default pin spacing during symbol generation itself so newly created parts follow a more readable layout automatically instead of manually repositioning pins afterward?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>When creating netlist files in other formats, OrCAD Capture 25.1 pops up an error prompt.</title><link>https://community.cadence.com/thread/65978?ContentTypeID=0</link><pubDate>Sun, 03 May 2026 10:25:24 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b8d03608-81a2-4811-949b-08c01ca67132</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/65978?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65978/when-creating-netlist-files-in-other-formats-orcad-capture-25-1-pops-up-an-error-prompt/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span&gt;Hi guys&lt;/span&gt;, I sometimes design schematics with OrCAD Capture and do PCB layout with P*DS Layout. Recently,&lt;/p&gt;
&lt;p&gt;I&amp;rsquo;ve found that OrCAD Capture 25.1 throws an error when generating netlist files in other formats.&lt;/p&gt;
&lt;p&gt;When I select Create Netlist &amp;rarr; Other, the error pops up.&lt;/p&gt;
&lt;p&gt;ERROR(ORNET-1143): 无法打开网表格式文件：C:\Cadence\SPB_25.1\tools\capture\网络形式\oraccel64.dll。&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Language preference in capture</title><link>https://community.cadence.com/thread/65971?ContentTypeID=0</link><pubDate>Thu, 30 Apr 2026 12:59:05 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b76cbffa-fde9-4098-8a7d-f4af616265a7</guid><dc:creator>edahub</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/65971?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65971/language-preference-in-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have upgraded to 25.1 version of OrcadX recently and observed that we can choose local language from preferences. Are there list of languages that OrcadX currently supports?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>