<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Allegro X Capture CIS - Recent Threads</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 14 Sep 2026 11:49:12 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis" /><item><title>Viewing datasheets in orcad cip</title><link>https://community.cadence.com/thread/66328?ContentTypeID=0</link><pubDate>Mon, 14 Sep 2026 11:49:12 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3f8ea280-3b7b-45ec-a201-a67ed08bcc4d</guid><dc:creator>digital1</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66328?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66328/viewing-datasheets-in-orcad-cip/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have an orcad cip database set up on my local machine using microsoft sql server and i have a collection of datasheets if i use the web address for the datasheets i am able to view the datasheet in the orcad cip database and by using the app from the parallel systems website i can view it in the capture schematic canvas by clicking the appropriate menu.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Unfortunately sometimes when i am on the road i dont have access to the internet so i am unable to view the datasheets&amp;nbsp; so i changed the web address of the datasheet to an address on my local machine such as this&amp;nbsp;C:\Cadence\CIP-E\Datasheets\Yageo\RC0402FR-073KL.pdf&amp;nbsp; i can now see them in the capture schematic canvass and cis but i cant view them in cip.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;What do i have to do to view them in both cip and capture and cis&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Why Are Identical Non-Database Parts Listed Separately in CIS BOM?</title><link>https://community.cadence.com/thread/66327?ContentTypeID=0</link><pubDate>Thu, 10 Sep 2026 17:46:34 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c3489618-2862-4d59-8fb3-26c9e15ce6aa</guid><dc:creator>LogicNet</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66327?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66327/why-are-identical-non-database-parts-listed-separately-in-cis-bom/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;Hi,&lt;br /&gt;&lt;br /&gt;In Capture, while generating a CIS BOM, I noticed that three resistor components placed from a schematic library (not linked to the CIS database) are listed as separate BOM entries even though they all have the same Value of 4.7k. I expected them to be combined into a single line item with the quantity updated accordingly. How does Capture determine whether non-database components are grouped together in a BOM, and is there a way to generate a compressed BOM for such parts?&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Using alternate schematic symbols</title><link>https://community.cadence.com/thread/66321?ContentTypeID=0</link><pubDate>Wed, 09 Sep 2026 19:37:44 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:50edf9dc-1f3a-4863-ad93-c447a46e9aea</guid><dc:creator>DP202605218058</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66321?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66321/using-alternate-schematic-symbols/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi all.&amp;nbsp; I want to replace a schematic symbol on schematic sheet with an alternate schematic symbol that is already assigned to the part.&amp;nbsp; I would think a &amp;#39;RMB &amp;gt; alternate schematic symbol&amp;#39; would be available, but I don&amp;#39;t see anything like that.&amp;nbsp; So how does one choose the alternate schematic symbol to place on a schematic sheet?&amp;nbsp; Again, the alternate schematic symbol is already assigned to the part; I can view it in CIP under the part number, I just can&amp;#39;t figure out how to place the alternate on a schematic.&amp;nbsp; OrCAD Capture V22.1&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>BOM GENERATOR ver2.6.9</title><link>https://community.cadence.com/thread/66318?ContentTypeID=0</link><pubDate>Tue, 08 Sep 2026 07:43:55 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c5e2727d-bf81-4d86-8f0d-8ab8214187a4</guid><dc:creator>JS202609088334</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66318?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66318/bom-generator-ver2-6-9/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Good day I&amp;rsquo;m having trouble about generating BOM the error say&lt;/p&gt;
&lt;p&gt;****Error!!Multiple Variant files present.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Control Bill Of Materials of different revision</title><link>https://community.cadence.com/thread/66312?ContentTypeID=0</link><pubDate>Fri, 04 Sep 2026 15:11:45 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:10160094-15a6-40fd-b695-2ec1fbcefc18</guid><dc:creator>Filo221</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66312?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66312/control-bill-of-materials-of-different-revision/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;I&amp;#39;m looking for some advice on BOM management and revision control.&lt;/p&gt;
&lt;p&gt;I use a multi-sheet Excel file, where each worksheet represents a different variant in the CIS. For every modification, I update the revision and date of the corresponding worksheet.&lt;/p&gt;
&lt;p&gt;We are talking about BOMs with approximately 1,500 components. Once the BOM has been exported from the CIS, what checks do you typically perform?&lt;/p&gt;
&lt;p&gt;Is there a tool available that can compare two BOMs and provide a detailed report of the differences?&lt;/p&gt;
&lt;p&gt;Thanks&amp;nbsp;&lt;/p&gt;
&lt;/div&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Hierarchical Design Challenge: New Ports Added!</title><link>https://community.cadence.com/thread/66306?ContentTypeID=0</link><pubDate>Thu, 03 Sep 2026 16:23:38 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7f3ed51e-83b4-4b24-8d94-2bbef4200956</guid><dc:creator>TechnoBobby</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66306?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66306/hierarchical-design-challenge-new-ports-added/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;A Buck Converter is implemented as a hierarchical block in the parent schematic.&lt;br /&gt;&lt;br /&gt;Initially, the child schematic contained only &lt;strong&gt;Vin, Vout, and PWM&lt;/strong&gt; ports, and the H-Block was already placed and connected.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:224px;max-width:389px;" height="224" src="https://community.cadence.com/resized-image/__size/778x448/__key/communityserver-discussions-components-files/109/SS1.png" width="389" alt=" " /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/SS2.png" alt=" " /&gt;&lt;br /&gt;Later, the design was expanded and two new ports were added to the child schematic:&amp;nbsp;&lt;strong&gt;PGOOD and&amp;nbsp;&lt;/strong&gt;&lt;strong&gt;Fault&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Screenshot-2026_2D00_09_2D00_03-214026.png" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/strong&gt;How would you update the existing H-Block in the parent schematic so the new ports become available?&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;A.&lt;/strong&gt; Delete and recreate the H-Block&lt;br /&gt;&lt;strong&gt;B.&lt;/strong&gt; Manually add and rename hierarchical pins&lt;br /&gt;&lt;strong&gt;C.&lt;/strong&gt;&amp;nbsp;Synchronize Up the Hierarchical Block&amp;nbsp;&lt;br /&gt;&lt;strong&gt;D.&lt;/strong&gt; &lt;span&gt;Synchronize&amp;nbsp;Down the Hierarchical Block&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Access and Review Designs with OrCAD X Cloud.</title><link>https://community.cadence.com/thread/66301?ContentTypeID=0</link><pubDate>Tue, 01 Sep 2026 06:10:07 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:37c7f184-7af3-41b1-96d4-f2adf4fabe23</guid><dc:creator>Jeet</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66301?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66301/access-and-review-designs-with-orcad-x-cloud/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;The web-based collaboration capabilities of OrCAD X Cloud help engineers, reviewers, and project stakeholders stay connected throughout the design process. Whether reviewing schematics, providing feedback, or validating PCB layouts, users can work together more efficiently while maintaining a single source of truth for the design.&lt;/div&gt;
&lt;p&gt;To access the OrCAD X Cloud workspace, follow these steps:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;
&lt;p&gt;Navigate to the&lt;span&gt;&amp;nbsp;&lt;/span&gt;&lt;strong&gt;pcb.cadence.com/dashboard&amp;#160;&lt;/strong&gt;website in a web browser.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Enter your login credentials to authenticate.&lt;/p&gt;
&lt;/li&gt;
&lt;li&gt;
&lt;p&gt;Upon successful login, your Cloud Workspace will open, granting you access to the web version of your&lt;span&gt;&amp;nbsp;&lt;/span&gt;&lt;strong&gt;Workspace&lt;/strong&gt;, as shown below:&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1788242950862v2.png" alt=" " /&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;&lt;/p&gt;
&lt;div&gt;Have you started using OrCAD X Cloud for your design reviews and collaboration workflows? Share your experiences and best practices&amp;nbsp;here!&lt;/div&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Tired of Repetitive Login Pop-ups?</title><link>https://community.cadence.com/thread/66300?ContentTypeID=0</link><pubDate>Tue, 01 Sep 2026 05:53:46 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fbd3d527-2192-469e-95bf-5fd347386333</guid><dc:creator>Renu Vibha</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66300?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66300/tired-of-repetitive-login-pop-ups/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Does the Cloud login prompt in OrCAD X Capture CIS interrupt your workflow every time you start the tool?&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Find the solution here:&lt;br /&gt;&lt;a href="https://ask.cadence.com/ASK/article-viewer?id=a1OPP000001SkfF2AS&amp;amp;pageName=article-viewer"&gt;&lt;em&gt;In OrCAD X Capture CIS, how do I disable the login pop-up that appears for Cloud services every time I start the tool?&lt;/em&gt;&lt;/a&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>What do ^ and ! mean in Intersheet References? Can they be removed?</title><link>https://community.cadence.com/thread/66292?ContentTypeID=0</link><pubDate>Thu, 27 Aug 2026 18:19:45 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:5dcdb081-8d84-41c0-aae2-93a74dca9061</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66292?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66292/what-do-and-mean-in-intersheet-references-can-they-be-removed/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;I noticed that OrCAD Capture adds &lt;code&gt;^&lt;/code&gt; and &lt;code&gt;!&lt;/code&gt; symbols in Intersheet References by default. I assume they indicate whether the referenced page is above or below the current page, but I&amp;#39;m not sure what their exact purpose is.&lt;br /&gt;&lt;br /&gt;Can someone explain what these symbols mean? Also, is there a way to remove them if they&amp;#39;re not needed? Has anyone customized this behavior in their designs?&lt;/p&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>25.1 HF005 - PDF Export/Printing in BW?</title><link>https://community.cadence.com/thread/66282?ContentTypeID=0</link><pubDate>Sat, 22 Aug 2026 09:14:37 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ad14b0e0-5068-4793-86d5-813054bd6910</guid><dc:creator>Ulf K</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/66282?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66282/25-1-hf005---pdf-export-printing-in-bw/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Greetings forum,&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;My desire is to print schematics in BW and have them printed with thinnest possible wire widths.&lt;/p&gt;
&lt;p&gt;For this, I have previously used CutePDF as print engine and Foxit PDF reader to view and from there print pages that I wanted.&lt;/p&gt;
&lt;p&gt;Earlier, Cadence seemed to use GhostScript engine for PDF generation. Now with 25.1 HF005 it seems that Cadence have&lt;/p&gt;
&lt;p&gt;written its own interface or embedded the GhostScript into the software. Anyway, there are no PDF options for quality in that&lt;/p&gt;
&lt;p&gt;interface.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;Now the print outs if using print to PDF are either in color with thick wires or when using Export-&amp;gt;PDF that the wires are BW but thick.&lt;/p&gt;
&lt;p&gt;I have looked around the the print setup menus for OrCADPS or CutePDF (or any other output format that is to direct&lt;/p&gt;
&lt;p&gt;prints to .PDF.) Regardless of me defining BW, I cannot get what I want.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;Having multiple versions of Cadence SPB in my computer, Windows also asks me if it should remove some of the OrCADPS&lt;/p&gt;
&lt;p&gt;relating to older versions (than 25.1) something that I do not dare to even consider, since I accidentally removed them&lt;/p&gt;
&lt;p&gt;earlier and it was not that easy to recreate them. This however perhaps a question that should be directed to the software build team.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;If there are any PDF setting that controls the generated width of graphic lines, please let me know.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Understanding the Auto Backup Feature in OrCAD Capture CIS</title><link>https://community.cadence.com/thread/66256?ContentTypeID=0</link><pubDate>Tue, 11 Aug 2026 11:11:31 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:dab78b3f-8acc-4f74-a10e-9fc76bf3365d</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66256?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66256/understanding-the-auto-backup-feature-in-orcad-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;OrCAD Capture CIS provides an &lt;strong&gt;Auto Backup (Multi-level Backup)&lt;/strong&gt; feature that helps protect users from losing unsaved design changes. This feature automatically creates design backup files when specific conditions are met, providing an additional safety net in the event of application crashes, system failures, or other unexpected interruptions.&lt;/p&gt;
&lt;p&gt;The &lt;strong&gt;Multi-level Backup Settings&lt;/strong&gt; dialog box can be accessed by selecting &lt;strong&gt;Options &amp;rarr; Auto Backup&lt;/strong&gt; from the main menu.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1786446507707v2.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;&lt;span data-teams="true"&gt;&lt;span class="fui-Primitive ___1gs1a2d f10pi13n f14t3ns0"&gt;&lt;span class="___164yu9v ftuwxu6 f1qdqbpl fua484e f1o6l1dn fac4klo frp1kbq f3wazqe f19l72ij fcsrh55 frnyhdv fyo61pj f1spqul0 f7dkd9s fkq5uzf f1x4fozf fwl63ro f1npyoe5 f10yrmu1 f1w45tcp f1rhua56 f18c6rdl f1e7lo8u f1dpi1ry f1vs2jsm f1o6uux1 f1nu0r7q fg0t3io f1x8dyll f2yyzyc f1sjbqdg fyzb71r fh1aahx f1oktu5 f1d3652t fed2bxt fpeluho f1e76dpb f1lwmlrd f1nri12l f1d705n1 f1jrvuk2 f11h0gum f1tandro fxjdbx7 f1hva1tl fsaoqmu f1w7c29l f1uakdsb f7jsfu7 f1hz9qas f1vmprsu fbmzazh f1oojlmx fpbf6y8 fy6vjqu fuo4419 fbzygsp fnuenae fw75flx f12oply1 fvyt4us f4ki1i fyy2ueq f1w3oopj fum67ou f1j64hbx f1a9cdrb f1q6iyvy f1s5r85c f920ium fhj6euq f30elfj f1kcike0 f1byno2r f5wk2nc fo3pyhm f1m95b1n fob93lq f9myhws fwkcdud f1a3p1vp" itemtype="http://schema.skype.com/AMSImage"&gt;&lt;/span&gt;&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;A backup is generated when&amp;nbsp;below conditions are satisfied:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;The design has been modified.&lt;/li&gt;
&lt;li&gt;The design has &lt;strong&gt;not&lt;/strong&gt; been manually saved within the configured backup interval.&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;&lt;strong&gt;Example&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;If the backup interval is set to &lt;strong&gt;10 minutes&lt;/strong&gt;:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;A user modifies the design at &lt;strong&gt;10:00 AM&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;If the design is manually saved before &lt;strong&gt;10:10 AM&lt;/strong&gt;, no .DBK backup file is created.&lt;/li&gt;
&lt;li&gt;If the design remains unsaved for 10 minutes after the modification, Capture automatically creates a &lt;strong&gt;.DBK (Design Backup)&lt;/strong&gt; file in the configured backup directory.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;span&gt;The &lt;strong&gt;Auto Backup (Multi-level Backup)&lt;/strong&gt; feature acts as a safety mechanism to protect users from losing unsaved design changes.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Hope you have tried it. &lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Share scenarios in which the backup feature helped saving your data from getting lost.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Happy learning!!&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Join us for a Syscap-Pulse Live AMA Session on Aug 5th at 7:30-8:30PM IST</title><link>https://community.cadence.com/thread/66245?ContentTypeID=0</link><pubDate>Wed, 05 Aug 2026 14:01:56 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ae031735-1da2-4cb9-9a52-5ded1e2cd77b</guid><dc:creator>Renu Vibha</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66245?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66245/join-us-for-a-syscap-pulse-live-ama-session-on-aug-5th-at-7-30-8-30pm-ist/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Explore the latest capabilities in System Capture and engage directly with Cadence experts on:&lt;/p&gt;
&lt;p&gt;&lt;span class="emoticon" data-url="https://community.cadence.com/cfs-file/__key/system/emoji/1f539.svg" title="Small blue diamond"&gt;&amp;#x1f539;&lt;/span&gt;&amp;nbsp;Team Design&lt;br /&gt;&amp;nbsp;&lt;span class="emoticon" data-url="https://community.cadence.com/cfs-file/__key/system/emoji/1f539.svg" title="Small blue diamond"&gt;&amp;#x1f539;&lt;/span&gt;&amp;nbsp;LiveBOM&lt;br /&gt;&amp;nbsp;&lt;span class="emoticon" data-url="https://community.cadence.com/cfs-file/__key/system/emoji/1f539.svg" title="Small blue diamond"&gt;&amp;#x1f539;&lt;/span&gt;&amp;nbsp;Unified Search&lt;/p&gt;
&lt;p&gt;Whether you&amp;#39;re looking to improve collaboration, streamline BOM management, or find information faster, this session is for you.&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Join the conversation,&lt;span&gt;&amp;nbsp;&lt;/span&gt;&lt;a href="https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pulse-edm/66218/pulse-live-ama-session-is-coming"&gt;here&lt;/a&gt;&lt;span&gt;&amp;nbsp;&lt;/span&gt;on Wednesday, Aug 5&lt;sup&gt;th&lt;/sup&gt;&lt;span&gt;&amp;nbsp;&lt;/span&gt;at 7:30-8:30PM IST&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Bring your questions. &amp;nbsp;Leave with answers.&lt;/strong&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Change Multiple Text Colors in OrCAD X Capture</title><link>https://community.cadence.com/thread/66243?ContentTypeID=0</link><pubDate>Wed, 05 Aug 2026 08:59:43 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:101fbdfd-d28c-49d7-a2de-f50832426a36</guid><dc:creator>Siri</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66243?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66243/change-multiple-text-colors-in-orcad-x-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Is there a way to change the colour of multiple text at once in OrCAD Capture?&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Thanks&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Browsable CIS link always opens in Microsoft Edge</title><link>https://community.cadence.com/thread/66217?ContentTypeID=0</link><pubDate>Wed, 29 Jul 2026 15:41:12 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f0d44af6-5292-4f03-8eb4-ac6364d5b8cb</guid><dc:creator>LogicNet</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66217?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66217/browsable-cis-link-always-opens-in-microsoft-edge/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;Hi all,&lt;br /&gt;&lt;br /&gt;I am using Capture CIS and have configured a property as Browsable, allowing users to click a link directly from CIS Explorer and open the associated document or webpage.&lt;br /&gt;The functionality works as expected, but whenever I click the link, it always opens in Microsoft Edge. On my system, I would prefer these links to open in Google Chrome instead.&lt;/p&gt;
&lt;p&gt;I checked the CIS configuration but could not find any setting that allows me to specify which browser should be used for browsable links.&lt;/p&gt;
&lt;p&gt;Is it possible to configure CIS to launch browsable links using a specific browser such as Chrome? &lt;br /&gt;&lt;br /&gt;Thanks!&lt;/p&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>SpaceMousen (3D Mouse) support</title><link>https://community.cadence.com/thread/66198?ContentTypeID=0</link><pubDate>Sat, 25 Jul 2026 23:15:08 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8ccdd827-a434-486c-9185-8ee3918e2c96</guid><dc:creator>JH202606267441</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66198?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66198/spacemousen-3d-mouse-support/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Has it been brought up that support for the 3D Connexion SpaceMouse would be really helpful for panning, rotating, and zooming both 2D and 3D UI. Please add support for using the SpaceMouse.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Leveraging Instance and Occurrence Annotation Modes in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66187?ContentTypeID=0</link><pubDate>Tue, 21 Jul 2026 19:28:40 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1581197c-f58d-40d0-a74a-0b0715c10d2e</guid><dc:creator>TechnoBobby</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66187?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66187/leveraging-instance-and-occurrence-annotation-modes-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;If you&amp;#39;re working with hierarchical designs in OrCAD Capture, you may have noticed both &lt;strong&gt;Instance&lt;/strong&gt; and &lt;strong&gt;Occurrence&lt;/strong&gt; annotation modes in the Annotate window.&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;What is the difference between Instance and Occurrence annotation modes?&lt;br /&gt;&lt;br /&gt;&lt;/strong&gt;The key difference lies in how reference designators are assigned in hierarchical designs.&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;a) Instance Mode&lt;/strong&gt; assigns reference designators at the component instance level and is commonly used for &lt;strong&gt;flat designs&lt;/strong&gt; or &lt;strong&gt;simple hierarchical designs&lt;/strong&gt;.&lt;br /&gt;&lt;strong&gt;b) Occurrence Mode&lt;/strong&gt; assigns reference designators at the occurrence level, allowing each use of a hierarchical block to have &lt;strong&gt;unique reference designators&lt;/strong&gt;.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1784661774380v3.png" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;The recommended annotation mode depends on the design structure. Understanding when to use each mode helps ensure unique reference designators across reused blocks and avoids manual renumbering effort.&lt;br /&gt;&lt;br /&gt;Another useful concept is the relationship between the&amp;nbsp;grey and yellow columns shown in the Property Editor. The grey column represents instance properties, while the yellow columns represent occurrence properties.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:300px;max-width:414px;" height="300" src="https://community.cadence.com/resized-image/__size/828x600/__key/communityserver-discussions-components-files/109/pastedimage1784661969614v4.png" width="414" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;Follow up questions do let us know!!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Is it possible to create inverted pins in the Part Editor?</title><link>https://community.cadence.com/thread/66164?ContentTypeID=0</link><pubDate>Wed, 15 Jul 2026 09:22:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7328848d-0be4-4cd9-af44-dccae3127489</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66164?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66164/is-it-possible-to-create-inverted-pins-in-the-part-editor/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span data-teams="true"&gt;Hi,&lt;br /&gt;&lt;br /&gt; I&amp;rsquo;m creating a new schematic symbol in the OrCAD Capture Part Editor and was wondering if it&amp;rsquo;s possible to define a pin as inverted directly in the Part Editor.&lt;br /&gt;If so, what&amp;rsquo;s the recommended way to create or display inverted pins while creating the symbol?&lt;br /&gt;&lt;br /&gt;Thanks.&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>ERROR  (ORCOMMN-12005) Unable to launch Orcad Capture.</title><link>https://community.cadence.com/thread/66152?ContentTypeID=0</link><pubDate>Thu, 09 Jul 2026 12:05:18 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fb050bee-c79c-4c35-83d2-0b5d903fb39d</guid><dc:creator>Shashank</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66152?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66152/error-orcommn-12005-unable-to-launch-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;strong&gt;ERROR&amp;nbsp; (ORCOMMN-12005) Unable to launch Orcad Capture. A valid license wasn found at the 5280@hostname license server. Update the license server configuration to include OrCAD Capture licenses&lt;/strong&gt;&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;I have installed &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-weight="bold" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal"&gt;OrCAD 25.1&lt;/span&gt; and configured the environment variables to point to the license server. Additionally, I have verified that ports &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-weight="bold" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal"&gt;5280&lt;/span&gt; and &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal" data-w-weight="bold"&gt;3000&lt;/span&gt; are in the listening state.&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;However, I am still encountering the attached error.&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;Could you please let me know if I have missed any configuration steps, or advise on how this issue can be resolved?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Conversion of  concept HDL symbol to .olb?</title><link>https://community.cadence.com/thread/66151?ContentTypeID=0</link><pubDate>Thu, 09 Jul 2026 11:11:39 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b7f5844f-cb5b-4874-ad40-1c6ecb3947a8</guid><dc:creator>BM202607094213</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/66151?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66151/conversion-of-concept-hdl-symbol-to-olb/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I have symbols in concept HDL format (.prt, .ptf, .css, .tag). How can I convert them to .olb?&lt;/p&gt;
&lt;p&gt;Is there any tool?&lt;/p&gt;
&lt;p&gt;i have tried to convert using Allegro project manager. am getting below attached error.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1783595430915v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;Kindly suggest the procedure.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Balkis&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How does OrCAD Capture decide which net alias is used in the PCB netlist?</title><link>https://community.cadence.com/thread/66132?ContentTypeID=0</link><pubDate>Fri, 03 Jul 2026 20:43:05 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cb4a4f53-253f-4b6d-b767-62a7b3d13f6a</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66132?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66132/how-does-orcad-capture-decide-which-net-alias-is-used-in-the-pcb-netlist/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;br /&gt;&lt;br /&gt;I have a schematic where a single net has multiple net aliases. For example, a power net is labeled as both VCC and +5V at different locations in the design. When creating the netlist for PCB, how does OrCAD Capture determine which net name is transferred to the PCB tool? Is there a way to explicitly control which alias is used in the generated netlist without removing the other net aliases?&lt;br /&gt;&lt;br /&gt;Thanks.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Leveraging Design Review &amp; Markups in OrCAD X Capture CIS 25.1</title><link>https://community.cadence.com/thread/66119?ContentTypeID=0</link><pubDate>Tue, 30 Jun 2026 14:10:41 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d43ac01e-d822-4ed9-8016-e39fa82255b5</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66119?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66119/leveraging-design-review-markups-in-orcad-x-capture-cis-25-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Collaboration plays a critical role in today&amp;rsquo;s schematic design workflows, especially when multiple engineers are working on the same project. Traditional feedback methods&amp;mdash;like emails or screenshots&amp;mdash;can often lead to miscommunication and delays.&lt;/p&gt;
&lt;p&gt;To address this, OrCAD X Capture CIS 25.1 introduces the Design Review and Markup feature, enabling a more streamlined and interactive review process directly within the schematic environment.&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;What is Design Review &amp;amp; Markup?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;The Design Review and Markup feature allows users to:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Add comments directly on the schematic canvas&lt;/li&gt;
&lt;li&gt;Highlight areas using graphical markups (rectangles and arrows)&lt;/li&gt;
&lt;li&gt;Tag team members for collaboration&lt;/li&gt;
&lt;li&gt;Embed review feedback within the design itself&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;This ensures that all stakeholders can view and act on feedback within the same design.&lt;br /&gt; &lt;br /&gt; &lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Add Comments &amp;amp; Markup&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Open your schematic in &lt;strong&gt;OrCAD X Capture CIS&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Go to &lt;strong&gt;Tools &amp;rarr; Markup&lt;/strong&gt; (opens Comments panel)&lt;/li&gt;
&lt;li&gt;Click &lt;strong&gt;New Comment&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Mark the area using:&lt;ul&gt;
&lt;li&gt;Rectangle ➝ highlight region&lt;/li&gt;
&lt;li&gt;Arrow ➝ point to object&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;Enter your comment (use &lt;strong&gt;@username&lt;/strong&gt; to tag users)&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Click &lt;strong&gt;Submit&lt;/strong&gt; &amp;rarr; Comment is saved in design&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Picture1.png" /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Review &amp;amp; Respond to Comments&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Open schematic and go to &lt;strong&gt;Tools &amp;rarr; Markup&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Select a comment &amp;rarr; Auto-zoom to location&lt;/li&gt;
&lt;li&gt;Add replies or update feedback&lt;/li&gt;
&lt;li&gt;Mark as &lt;strong&gt;Resolved&lt;/strong&gt; once addressed&lt;br /&gt;&lt;br /&gt;&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Picture2.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;&lt;img style="max-height:400px;max-width:500px;" alt=" " src="https://community.cadence.com/resized-image/__size/1000x800/__key/communityserver-discussions-components-files/109/Picture3.png" /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;The Design Review and Markup feature in OrCAD X Capture CIS 25.1 brings collaboration directly into the schematic, enabling teams to communicate more efficiently and reduce design iteration cycles.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt; &lt;br /&gt;&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/66098?ContentTypeID=0</link><pubDate>Wed, 24 Jun 2026 16:37:25 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b70eb17f-a06d-4859-babe-7f9e3327b886</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>8</slash:comments><comments>https://community.cadence.com/thread/66098?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I recently encountered an odd software bug while drawing schematics in OrCAD Capture.&lt;/p&gt;
&lt;p&gt;1. Create a blank OrCAD Capture project, and add two schematic pages: Page1 and Page2.&lt;/p&gt;
&lt;p&gt;2. Place two off-page connectors on Page1 with the net names A+9 and A+_ respectively.&lt;/p&gt;
&lt;p&gt;3. Place three off-page connectors on Page2 with the net names A+9, A+_ and A_ respectively.&lt;br /&gt;(The leading letter &amp;quot;A&amp;quot; can be replaced with any alphabetic character.)&lt;/p&gt;
&lt;p&gt;Right-click any off-page connector and select the Signals option to bring up the signal navigation list. You will see disordered, incorrect jump targets in this list. Nevertheless, the exported final netlist contains fully correct electrical connections as expected.&lt;/p&gt;
&lt;p&gt;You can test the jump function by sequentially clicking every off-page connector on both schematic pages to reproduce this defect.&lt;/p&gt;
&lt;p&gt;This makes people mistakenly believe that the signals are not connected when actually checking the wiring relationships in the schematic.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="color:#0000ff;"&gt;&lt;/span&gt;&lt;/p&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;&lt;span style="color:#ff0000;"&gt;Supplemental Note: This issue can only be reproduced after launching PCB Editor or PCB Presto.&lt;/span&gt;&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Increasing Icon/menu size in capture</title><link>https://community.cadence.com/thread/66096?ContentTypeID=0</link><pubDate>Wed, 24 Jun 2026 07:11:28 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1da79788-a10e-49db-8df8-ea4138503957</guid><dc:creator>Siri</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66096?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66096/increasing-icon-menu-size-in-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;/p&gt;
&lt;p&gt;I would like to increase the icon size in OrCAD Capture. Is there a setting available to adjust the icon size?&lt;/p&gt;
&lt;p&gt;Please let me know the steps if this is possible.&lt;/p&gt;
&lt;p&gt;Thanks in advance.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Hierarchical design cut paste causing refdes changes</title><link>https://community.cadence.com/thread/66090?ContentTypeID=0</link><pubDate>Mon, 22 Jun 2026 05:17:45 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9bfa6b3b-90b8-4c1c-829e-2cdbcf14c1b4</guid><dc:creator>BoardIQ</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/66090?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66090/hierarchical-design-cut-paste-causing-refdes-changes/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;We are using Allegro Capture CIS ver 22.1.&lt;/p&gt;
&lt;p&gt;My design is using hierarchical blocks across several pages. When I move a hierarchical block from one page to another by Cut + Paste, the refdes inside the hierarchical block gets changed. This affects our layout of the PCB.&lt;/p&gt;
&lt;p&gt;Strange thing about this is that it affects only few hierarchical blocks, whereas it works fine with some hierarchical blocks.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Does anyone else face a similar problem?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>I am not able to generate pdf in allegro dehdl 24.1</title><link>https://community.cadence.com/thread/66084?ContentTypeID=0</link><pubDate>Thu, 18 Jun 2026 05:52:08 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:6061d667-c0fc-4df9-8b92-322ebb79dcea</guid><dc:creator>Shashank</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66084?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66084/i-am-not-able-to-generate-pdf-in-allegro-dehdl-24-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have below licenses,&lt;/p&gt;
&lt;p&gt;Allegro Library Authoring (PCB Librarian)&lt;/p&gt;
&lt;p&gt;Allegro PCB Designer [Schematic]&lt;/p&gt;
&lt;p&gt;I am using&amp;nbsp;&lt;span style="color:#ff6600;"&gt;&lt;span style="color:#000000;"&gt;Allegro PCB Designer [Schematic],&lt;/span&gt;&amp;nbsp;&lt;span style="color:#000000;"&gt;and trying to export pdf by going to&lt;span&gt;&amp;nbsp;&lt;/span&gt;FILE-&amp;gt;PUBLISH PDF&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="color:#000000;"&gt;But i am getting below error,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;ERROR(SPCOCN-152): The license for this feature could not be&lt;br /&gt;checked out because it is temporarily unavailable. Contact&lt;br /&gt;your administrator to check the license server.&lt;/p&gt;
&lt;p&gt;How can i resolve this and generate a pdf.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>