<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Allegro X Capture CIS - Recent Threads</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>SpaceMousen (3D Mouse) support</title><link>https://community.cadence.com/thread/66198?ContentTypeID=0</link><pubDate>Sat, 25 Jul 2026 23:15:08 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8ccdd827-a434-486c-9185-8ee3918e2c96</guid><dc:creator>JH202606267441</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66198?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66198/spacemousen-3d-mouse-support/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Has it been brought up that support for the 3D Connexion SpaceMouse would be really helpful for panning, rotating, and zooming both 2D and 3D UI. Please add support for using the SpaceMouse.&amp;nbsp;&lt;/p&gt;</description></item><item><title>RE: SpaceMousen (3D Mouse) support</title><link>https://community.cadence.com/thread/1409001?ContentTypeID=1</link><pubDate>Tue, 28 Jul 2026 07:19:18 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:0b279bc5-247e-4871-8875-72c9526bb5e5</guid><dc:creator>rg13</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1409001?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66198/spacemousen-3d-mouse-support/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;An enhancement Cadence change request is already in place for this requirement.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Leveraging Instance and Occurrence Annotation Modes in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66187?ContentTypeID=0</link><pubDate>Tue, 21 Jul 2026 19:28:40 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1581197c-f58d-40d0-a74a-0b0715c10d2e</guid><dc:creator>TechnoBobby</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66187?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66187/leveraging-instance-and-occurrence-annotation-modes-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;If you&amp;#39;re working with hierarchical designs in OrCAD Capture, you may have noticed both &lt;strong&gt;Instance&lt;/strong&gt; and &lt;strong&gt;Occurrence&lt;/strong&gt; annotation modes in the Annotate window.&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;What is the difference between Instance and Occurrence annotation modes?&lt;br /&gt;&lt;br /&gt;&lt;/strong&gt;The key difference lies in how reference designators are assigned in hierarchical designs.&lt;br /&gt;&lt;br /&gt;&lt;strong&gt;a) Instance Mode&lt;/strong&gt; assigns reference designators at the component instance level and is commonly used for &lt;strong&gt;flat designs&lt;/strong&gt; or &lt;strong&gt;simple hierarchical designs&lt;/strong&gt;.&lt;br /&gt;&lt;strong&gt;b) Occurrence Mode&lt;/strong&gt; assigns reference designators at the occurrence level, allowing each use of a hierarchical block to have &lt;strong&gt;unique reference designators&lt;/strong&gt;.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1784661774380v3.png" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;The recommended annotation mode depends on the design structure. Understanding when to use each mode helps ensure unique reference designators across reused blocks and avoids manual renumbering effort.&lt;br /&gt;&lt;br /&gt;Another useful concept is the relationship between the&amp;nbsp;grey and yellow columns shown in the Property Editor. The grey column represents instance properties, while the yellow columns represent occurrence properties.&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:300px;max-width:414px;" height="300" src="https://community.cadence.com/resized-image/__size/828x600/__key/communityserver-discussions-components-files/109/pastedimage1784661969614v4.png" width="414" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;Follow up questions do let us know!!&lt;/p&gt;</description></item><item><title>Is it possible to create inverted pins in the Part Editor?</title><link>https://community.cadence.com/thread/66164?ContentTypeID=0</link><pubDate>Wed, 15 Jul 2026 09:22:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7328848d-0be4-4cd9-af44-dccae3127489</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66164?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66164/is-it-possible-to-create-inverted-pins-in-the-part-editor/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span data-teams="true"&gt;Hi,&lt;br /&gt;&lt;br /&gt; I&amp;rsquo;m creating a new schematic symbol in the OrCAD Capture Part Editor and was wondering if it&amp;rsquo;s possible to define a pin as inverted directly in the Part Editor.&lt;br /&gt;If so, what&amp;rsquo;s the recommended way to create or display inverted pins while creating the symbol?&lt;br /&gt;&lt;br /&gt;Thanks.&lt;/span&gt;&lt;/p&gt;</description></item><item><title>RE: Is it possible to create inverted pins in the Part Editor?</title><link>https://community.cadence.com/thread/1408919?ContentTypeID=1</link><pubDate>Thu, 16 Jul 2026 10:04:33 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4fa92625-dbeb-4bcf-9d12-75933b8062e6</guid><dc:creator>TechnoBobby</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408919?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66164/is-it-possible-to-create-inverted-pins-in-the-part-editor/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi &lt;a href="/members/logicnet"&gt;LogicNet&lt;/a&gt;&amp;nbsp;,&lt;br /&gt;&lt;br /&gt;Yes, it is possible to represent an inverted (active-low) pin in the OrCAD Capture Part Editor.&lt;br /&gt;&lt;br /&gt;A negative/inverted pin can be displayed in one of the following ways:&lt;br /&gt;&lt;br /&gt;a) Using a DOT pin shape: Open the pin properties in the Part Editor and set the Shape field to DOT. This places the inversion bubble on the pin, which is the standard symbol representation for an active-low signal.&lt;br /&gt;&lt;br /&gt;b) Using a bar over the pin name: In the pin properties, edit the pin name and add a backslash (\) after each character that should be shown with an overbar. For example, entering O\U\T\ will display the pin name with a bar over OUT.&lt;br /&gt;&lt;br /&gt;Both methods can be configured directly in the source library symbol within the Part Editor.&lt;br /&gt;&lt;br /&gt;For detailed steps and screenshots, please refer to the following article:&lt;br /&gt;Title: How to indicate that a pin is inverted or negative by placing a bar over its name in Capture&lt;br /&gt;URL: &lt;a href="https://ask.cadence.com/ASK/article-viewer?id=a1Od0000000nYCTEA2&amp;amp;pageName=article-viewer"&gt;https://ask.cadence.com/ASK/article-viewer?id=a1Od0000000nYCTEA2&amp;amp;pageName=article-viewer&lt;/a&gt;&lt;br /&gt;&lt;br /&gt;I hope this helps!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Conversion of  concept HDL symbol to .olb?</title><link>https://community.cadence.com/thread/1408893?ContentTypeID=1</link><pubDate>Fri, 10 Jul 2026 08:51:39 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:214ccace-45e7-4c8b-8f86-019cc5892647</guid><dc:creator>BM202607094213</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408893?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66151/conversion-of-concept-hdl-symbol-to-olb/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Thanks for repsonse.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;How can I get access to &amp;quot;&lt;span&gt;PCB_librarian_expert license&amp;quot; does it comes with package of allegro PCB editor?&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Regards,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Balkis&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Conversion of  concept HDL symbol to .olb?</title><link>https://community.cadence.com/thread/66151?ContentTypeID=0</link><pubDate>Thu, 09 Jul 2026 11:11:39 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b7f5844f-cb5b-4874-ad40-1c6ecb3947a8</guid><dc:creator>BM202607094213</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66151?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66151/conversion-of-concept-hdl-symbol-to-olb/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;I have symbols in concept HDL format (.prt, .ptf, .css, .tag). How can I convert them to .olb?&lt;/p&gt;
&lt;p&gt;Is there any tool?&lt;/p&gt;
&lt;p&gt;i have tried to convert using Allegro project manager. am getting below attached error.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1783595430915v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;Kindly suggest the procedure.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Regards,&lt;/p&gt;
&lt;p&gt;Balkis&lt;/p&gt;</description></item><item><title>RE: Conversion of  concept HDL symbol to .olb?</title><link>https://community.cadence.com/thread/1408892?ContentTypeID=1</link><pubDate>Fri, 10 Jul 2026 08:47:15 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3f216023-287e-4580-b500-0a8e6635d331</guid><dc:creator>rg13</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408892?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66151/conversion-of-concept-hdl-symbol-to-olb/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;If you use Project manager, then you can choose to convert your DEHDL library part to Capture part. However, as described above PCB_librarian_expert license is needed.&lt;/p&gt;
&lt;p&gt;Menu is Tools &amp;gt; Library Tools &amp;gt; Export&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: ERROR  (ORCOMMN-12005) Unable to launch Orcad Capture.</title><link>https://community.cadence.com/thread/1408890?ContentTypeID=1</link><pubDate>Fri, 10 Jul 2026 06:13:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:95816a6e-0867-478f-b5b3-1a81e4e66977</guid><dc:creator>Jeet</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408890?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66152/error-orcommn-12005-unable-to-launch-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Can you&amp;nbsp;check if CDS_LIC_FILE is configured properly in Environment Variables ?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>ERROR  (ORCOMMN-12005) Unable to launch Orcad Capture.</title><link>https://community.cadence.com/thread/66152?ContentTypeID=0</link><pubDate>Thu, 09 Jul 2026 12:05:18 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:fb050bee-c79c-4c35-83d2-0b5d903fb39d</guid><dc:creator>Shashank</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66152?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66152/error-orcommn-12005-unable-to-launch-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;strong&gt;ERROR&amp;nbsp; (ORCOMMN-12005) Unable to launch Orcad Capture. A valid license wasn found at the 5280@hostname license server. Update the license server configuration to include OrCAD Capture licenses&lt;/strong&gt;&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;I have installed &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-weight="bold" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal"&gt;OrCAD 25.1&lt;/span&gt; and configured the environment variables to point to the license server. Additionally, I have verified that ports &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-weight="bold" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal"&gt;5280&lt;/span&gt; and &lt;span class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-inline="" data-w-whitespace="linebreaks" data-w-wrap="normal" data-w-weight="bold"&gt;3000&lt;/span&gt; are in the listening state.&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;However, I am still encountering the attached error.&lt;/p&gt;
&lt;p class="zlAe0W_TextBase zlAe0W_Text" data-w-component="text" data-w-wrap="normal"&gt;Could you please let me know if I have missed any configuration steps, or advise on how this issue can be resolved?&lt;/p&gt;</description></item><item><title>Default shortcut keys are not working</title><link>https://community.cadence.com/thread/65933?ContentTypeID=0</link><pubDate>Thu, 16 Apr 2026 18:38:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:23cf81fb-a3fc-43db-9a61-5877e30cdd3c</guid><dc:creator>Siri</dc:creator><slash:comments>3</slash:comments><comments>https://community.cadence.com/thread/65933?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65933/default-shortcut-keys-are-not-working/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span&gt;1. Close Capture if already Running.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;2. Open and Edit in Notepad (or another text editor) the file located at C:Cadence/SPB_23.1/tools/bin/&lt;/span&gt;&lt;span&gt;orCEFSettings.ini&lt;/span&gt;&lt;br /&gt;&lt;span&gt;3. Add following line in this file :&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;lang=en-US&lt;/span&gt;&lt;br /&gt;&lt;br /&gt;&lt;span&gt;4. Save the file.&lt;/span&gt;&lt;br /&gt;&lt;span&gt;5. Run Capture.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Also I have renamed cdssetup folder and the issue still persists.&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Can anyone let me know what could be the reason.&lt;/span&gt;&lt;/p&gt;</description></item><item><title>RE: Default shortcut keys are not working</title><link>https://community.cadence.com/thread/1408882?ContentTypeID=1</link><pubDate>Wed, 08 Jul 2026 21:25:27 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3360524c-6415-4aea-98f3-00d317571ca3</guid><dc:creator>passedpawn</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408882?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/65933/default-shortcut-keys-are-not-working/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I&amp;#39;ve had this exact thing happen many times.&amp;nbsp; I did report it to Cadence.&amp;nbsp; Restarting the software fixes temporarily.&amp;nbsp; &amp;nbsp;I have not discovered the cause.&amp;nbsp;&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/1408854?ContentTypeID=1</link><pubDate>Tue, 07 Jul 2026 14:10:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cf3a81a0-77de-4e60-a06f-7bc2b9cf8bb2</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408854?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I would like to provide additional test results. Today I tested the exact same project file on OrCAD 16.6, and the cross-sheet navigation works correctly without this bug.&lt;/p&gt;
&lt;p&gt;Could someone help me log a CCR ticket for this issue? I hope this defect can be fixed in the upcoming hotfix releases. Thank you very much!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/66098?ContentTypeID=0</link><pubDate>Wed, 24 Jun 2026 16:37:25 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b70eb17f-a06d-4859-babe-7f9e3327b886</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>7</slash:comments><comments>https://community.cadence.com/thread/66098?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I recently encountered an odd software bug while drawing schematics in OrCAD Capture.&lt;/p&gt;
&lt;p&gt;1. Create a blank OrCAD Capture project, and add two schematic pages: Page1 and Page2.&lt;/p&gt;
&lt;p&gt;2. Place two off-page connectors on Page1 with the net names A+9 and A+_ respectively.&lt;/p&gt;
&lt;p&gt;3. Place three off-page connectors on Page2 with the net names A+9, A+_ and A_ respectively.&lt;br /&gt;(The leading letter &amp;quot;A&amp;quot; can be replaced with any alphabetic character.)&lt;/p&gt;
&lt;p&gt;Right-click any off-page connector and select the Signals option to bring up the signal navigation list. You will see disordered, incorrect jump targets in this list. Nevertheless, the exported final netlist contains fully correct electrical connections as expected.&lt;/p&gt;
&lt;p&gt;You can test the jump function by sequentially clicking every off-page connector on both schematic pages to reproduce this defect.&lt;/p&gt;
&lt;p&gt;This makes people mistakenly believe that the signals are not connected when actually checking the wiring relationships in the schematic.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="color:#0000ff;"&gt;&lt;/span&gt;&lt;/p&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;
&lt;div&gt;&lt;span style="color:#ff0000;"&gt;Supplemental Note: This issue can only be reproduced after launching PCB Editor or PCB Presto.&lt;/span&gt;&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;
&lt;/div&gt;</description></item><item><title>RE: In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/1408849?ContentTypeID=1</link><pubDate>Tue, 07 Jul 2026 04:20:26 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e9dfcfc9-529c-46ed-9308-c5022aa85393</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408849?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi Jon Lee，&lt;/p&gt;
&lt;p&gt;In practice, it is quite common to include plus (+) or minus (-) signs within signal and power net names to denote polarity instead of using P or N. Moreover, the plus sign is not defined as an illegal character for naming in OrCAD. This naming syntax works without any issues on EDA tools from other vendors. I am confused why OrCAD fails to support this standard practice, and it makes me wonder if OrCAD is inferior to competing EDA software in this aspect. Additionally, treating the plus symbol inside a net name as an arithmetic operator is fundamentally a flawed design logic.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/1408848?ContentTypeID=1</link><pubDate>Tue, 07 Jul 2026 03:31:14 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ce74ffaf-2b8b-40ef-84f1-c069e10303f6</guid><dc:creator>Jon Lee</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/1408848?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;The problem lies with the &amp;quot;+&amp;quot; character; you can understand it as the character not being supported; it&amp;#39;s not exactly a bug.&lt;/p&gt;
&lt;p&gt;A+9 is equivalent to A9&lt;br /&gt;A+_ is equivalent to A_&lt;br /&gt;It can be understood as if the &amp;quot;+&amp;quot; character does not exist.&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;Fixing this is not recommended; it can cause issues in certain types of searches, such as those involving regular expressions.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: How does OrCAD Capture decide which net alias is used in the PCB netlist?</title><link>https://community.cadence.com/thread/1408841?ContentTypeID=1</link><pubDate>Mon, 06 Jul 2026 05:33:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:982ce48e-0f1c-4431-bd57-b4098d6f173f</guid><dc:creator>Jeet</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408841?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66132/how-does-orcad-capture-decide-which-net-alias-is-used-in-the-pcb-netlist/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;PCB Netlist encounters multiple names for a single net, higher-priority aliases override lower priority aliases. Priority is determined by the source of the name, ranked as follows:&lt;/p&gt;
&lt;div&gt;&amp;nbsp;Lowest:&lt;/div&gt;
&lt;div&gt;&amp;bull; &amp;nbsp; &amp;nbsp; &amp;nbsp;System-generated names&lt;/div&gt;
&lt;div&gt;&amp;bull; &amp;nbsp; &amp;nbsp; &amp;nbsp;Aliases&lt;/div&gt;
&lt;div&gt;&amp;bull; &amp;nbsp; &amp;nbsp; &amp;nbsp;Power object names&lt;/div&gt;
&lt;div&gt;&amp;bull; &amp;nbsp; &amp;nbsp; &amp;nbsp;Off-page connectors&lt;/div&gt;
&lt;div&gt;&amp;bull; &amp;nbsp; &amp;nbsp; &amp;nbsp;Hierarchical port names&lt;/div&gt;
&lt;div&gt;&amp;nbsp;Highest:&lt;/div&gt;
&lt;div&gt;&amp;bull; &amp;nbsp; &amp;nbsp; &amp;nbsp;Named nets&lt;/div&gt;
&lt;div&gt;&amp;nbsp;&lt;/div&gt;
&lt;div&gt;&amp;nbsp;Any remaining conflicts among net names are resolved according to the following rules:&lt;/div&gt;
&lt;div&gt;&amp;bull; The net name closest to the &amp;quot;root&amp;quot; of the project takes precedence over those further away.&lt;/div&gt;
&lt;div&gt;&amp;bull; If the net is a bus, the net alias assigned to the greatest number of bus members has the highest priority.&lt;/div&gt;
&lt;div&gt;&amp;bull; Among net names of equal precedence, priority follows alphabetical order.&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>How does OrCAD Capture decide which net alias is used in the PCB netlist?</title><link>https://community.cadence.com/thread/66132?ContentTypeID=0</link><pubDate>Fri, 03 Jul 2026 20:43:05 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:cb4a4f53-253f-4b6d-b767-62a7b3d13f6a</guid><dc:creator>LogicNet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/66132?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66132/how-does-orcad-capture-decide-which-net-alias-is-used-in-the-pcb-netlist/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi,&lt;br /&gt;&lt;br /&gt;I have a schematic where a single net has multiple net aliases. For example, a power net is labeled as both VCC and +5V at different locations in the design. When creating the netlist for PCB, how does OrCAD Capture determine which net name is transferred to the PCB tool? Is there a way to explicitly control which alias is used in the generated netlist without removing the other net aliases?&lt;br /&gt;&lt;br /&gt;Thanks.&lt;/p&gt;</description></item><item><title>RE: In OrCAD Capture 25.1, certain naming formats for off-page connectors cause abnormal jumps in the Signals navigation function.</title><link>https://community.cadence.com/thread/1408837?ContentTypeID=1</link><pubDate>Sun, 05 Jul 2026 15:12:30 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:31185e44-3b02-447c-a368-90092eca4591</guid><dc:creator>Zhifeng Jin</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408837?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66098/in-orcad-capture-25-1-certain-naming-formats-for-off-page-connectors-cause-abnormal-jumps-in-the-signals-navigation-function/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;As an additional note, this bug still exists in OrCAD Capture 25.1 HF040, yet it seems no one has paid attention to this &lt;span&gt;bug&lt;/span&gt;. In my opinion, this is actually a fairly critical bug.&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/1png.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/6011.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/1408821?ContentTypeID=1</link><pubDate>Wed, 01 Jul 2026 11:09:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:04b2d93f-f017-4a0b-9550-d13f4894b6fb</guid><dc:creator>Ulf K</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408821?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;It is the menu box itself I was referring to. When someone wants to place an arbitrary test and want to use eg. Courier, the text box in the add-text-canvas displays (Cadence) proportional text like tms roman, arial etc. This font cannot be changed. It is only possible to see the resulting alignment when having opted for courier only after the text has been placed in the schematic drawing. If the alignment (like having (white) spaces is wrong, the only way to correct it is to edit the text and in that edit box add or remove the (white) spaces.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66059?ContentTypeID=0</link><pubDate>Wed, 10 Jun 2026 13:41:35 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8385581c-5ec8-42d3-b4ef-68ce8d3c5516</guid><dc:creator>Jeet</dc:creator><slash:comments>6</slash:comments><comments>https://community.cadence.com/thread/66059?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Starting with version 25.1, you can save and reuse Design Template settings to maintain consistency across projects. Design Template allows you to define default settings for new schematic designs, including fonts for various schematic objects, title block information, page size, grid references, and more.&lt;/p&gt;
&lt;p&gt;To save and reuse Design Template settings, follow the given steps-&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Navigate to &lt;strong&gt;Options&lt;/strong&gt; &amp;gt; &lt;strong&gt;Design Template&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;Customize the settings as required, including fonts, page size, title block, grid references, and other parameters.&lt;/li&gt;
&lt;li&gt;Once customization is complete, click Save. A dialog box will prompt you to save the configuration as a .dtp file at your preferred location.&lt;/li&gt;
&lt;li&gt;To apply the saved settings later, click Load in the Design Template dialog box and select the saved .dtp file from the desired location.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1781098685237v1.png" /&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This feature allows designers to reuse design properties across new schematic designs, eliminating the need for redundant redefinition. Additionally, it enables seamless sharing of template files among teams and ensures consistent formatting in&amp;nbsp;designs.&lt;/p&gt;</description></item><item><title>RE: Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/1408815?ContentTypeID=1</link><pubDate>Wed, 01 Jul 2026 06:13:31 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:577e4718-3a76-4cdd-9b68-cdd75ebbd6fe</guid><dc:creator>Jeet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408815?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Ulf,&lt;/p&gt;
&lt;p&gt;Currently these are the available fonts in Place &amp;gt; Text as shown below-&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1782886212741v1.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;As per your suggestion Cadence should add a feature by which designers can add a Text apart from a single word correct or you are looking for a particular font named &lt;span&gt;Andale Mono&lt;/span&gt;?&lt;/p&gt;
&lt;p&gt;Let me know if I am missing anything.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Leveraging Design Review &amp; Markups in OrCAD X Capture CIS 25.1</title><link>https://community.cadence.com/thread/66119?ContentTypeID=0</link><pubDate>Tue, 30 Jun 2026 14:10:41 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:d43ac01e-d822-4ed9-8016-e39fa82255b5</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66119?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66119/leveraging-design-review-markups-in-orcad-x-capture-cis-25-1/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Collaboration plays a critical role in today&amp;rsquo;s schematic design workflows, especially when multiple engineers are working on the same project. Traditional feedback methods&amp;mdash;like emails or screenshots&amp;mdash;can often lead to miscommunication and delays.&lt;/p&gt;
&lt;p&gt;To address this, OrCAD X Capture CIS 25.1 introduces the Design Review and Markup feature, enabling a more streamlined and interactive review process directly within the schematic environment.&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;What is Design Review &amp;amp; Markup?&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;The Design Review and Markup feature allows users to:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Add comments directly on the schematic canvas&lt;/li&gt;
&lt;li&gt;Highlight areas using graphical markups (rectangles and arrows)&lt;/li&gt;
&lt;li&gt;Tag team members for collaboration&lt;/li&gt;
&lt;li&gt;Embed review feedback within the design itself&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;This ensures that all stakeholders can view and act on feedback within the same design.&lt;br /&gt; &lt;br /&gt; &lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Add Comments &amp;amp; Markup&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Open your schematic in &lt;strong&gt;OrCAD X Capture CIS&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Go to &lt;strong&gt;Tools &amp;rarr; Markup&lt;/strong&gt; (opens Comments panel)&lt;/li&gt;
&lt;li&gt;Click &lt;strong&gt;New Comment&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Mark the area using:&lt;ul&gt;
&lt;li&gt;Rectangle ➝ highlight region&lt;/li&gt;
&lt;li&gt;Arrow ➝ point to object&lt;/li&gt;
&lt;/ul&gt;
&lt;/li&gt;
&lt;li&gt;Enter your comment (use &lt;strong&gt;@username&lt;/strong&gt; to tag users)&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Click &lt;strong&gt;Submit&lt;/strong&gt; &amp;rarr; Comment is saved in design&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Picture1.png" /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Review &amp;amp; Respond to Comments&lt;/strong&gt;&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Open schematic and go to &lt;strong&gt;Tools &amp;rarr; Markup&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;Select a comment &amp;rarr; Auto-zoom to location&lt;/li&gt;
&lt;li&gt;Add replies or update feedback&lt;/li&gt;
&lt;li&gt;Mark as &lt;strong&gt;Resolved&lt;/strong&gt; once addressed&lt;br /&gt;&lt;br /&gt;&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/Picture2.png" /&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt;&lt;img style="max-height:400px;max-width:500px;" alt=" " src="https://community.cadence.com/resized-image/__size/1000x800/__key/communityserver-discussions-components-files/109/Picture3.png" /&gt;&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;The Design Review and Markup feature in OrCAD X Capture CIS 25.1 brings collaboration directly into the schematic, enabling teams to communicate more efficiently and reduce design iteration cycles.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;br /&gt; &lt;br /&gt;&amp;nbsp;&lt;/p&gt;</description></item><item><title>RE: Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/1408804?ContentTypeID=1</link><pubDate>Mon, 29 Jun 2026 11:00:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:a98b7705-7c77-4b26-9363-6e26c5431df2</guid><dc:creator>Ulf K</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408804?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Andale Dot/Mono is available for download as TTF. I always install it and specify it for RefDes, Component values, pin names, pin numbers, net names (or in general *any* other text where it is important to distinguish between zero and the letter &amp;quot;O&amp;quot;). For the drawing header, I use Cadence suggested fonts.&lt;/p&gt;
&lt;p&gt;When installing Cadence tools, Andale fonts are defined in schematic templates. I use one pt larger for Refdes than for other texts in the drawings.&lt;/p&gt;
&lt;p&gt;BTW: When adding eg. informative texts, selecting (fixed space) Courier makes it easy to create small tables. But the Cadence &amp;quot;Add text&amp;quot; canvas text box uses a proportional text font. The example below is what one would want:&lt;/p&gt;
&lt;p&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;Information Header&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;=========================&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;Row 1 column 2 column 3&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span style="font-family:&amp;#39;courier new&amp;#39;, courier;"&gt;Row 2 column 2 column 3&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Thus, it is possible to see alignment errors only after the text is placed in the schematic drawing. Suggestion: Make it possible to change the input text font format to Courier as WYSIWYG option already in the canvas.&amp;nbsp;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/1408798?ContentTypeID=1</link><pubDate>Mon, 29 Jun 2026 05:57:00 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3b475af1-958f-4a8e-b4cc-00355b6ae41c</guid><dc:creator>Jeet</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408798?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Ulf, Thanks for the suggestion, any specific requirements to use this font in schematic design ?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>