<?xml version="1.0" encoding="UTF-8" ?>
<?xml-stylesheet type="text/xsl" href="https://community.cadence.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/"><channel><title>Allegro X Capture CIS - Recent Threads</title><link>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis</link><description /><dc:language>en-US</dc:language><generator>Telligent Community 12</generator><item><title>OrCAD Capture annotation issues for a heterogenous part in a hierarchical design</title><link>https://community.cadence.com/thread/66067?ContentTypeID=0</link><pubDate>Sat, 13 Jun 2026 03:26:16 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:7138f46e-0d0d-4646-8714-96ee5bef9967</guid><dc:creator>SF202503203610</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66067?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66067/orcad-capture-annotation-issues-for-a-heterogenous-part-in-a-hierarchical-design/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;I have a hierarchical block that is used 64 times.&amp;nbsp; Within that block I have a quad opamp that was pulled from the included OrCAD library.&amp;nbsp; The reference designators are U?A, U?B, U?C, U?D.&amp;nbsp; When I annotate this block, (Update Selection is selected). I do not get the annotation that I desire.&amp;nbsp; I want&lt;/p&gt;
&lt;p&gt;Instance 1:&amp;nbsp; U1A, U1B, U1C, U1D&lt;/p&gt;
&lt;p&gt;Instance 2:&amp;nbsp; U2A, U2B, U2C, U2D&lt;/p&gt;
&lt;p&gt;....&lt;/p&gt;
&lt;p&gt;Instance 64:&amp;nbsp; U64A, U64B, U64C, U64D&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;but what I am getting is&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Instance 1: U1A, U2B, U2A, U2C&lt;/p&gt;
&lt;p&gt;Instance 2: U1B, U3A, U2D, U3B&lt;/p&gt;
&lt;p&gt;etc&lt;/p&gt;
&lt;p&gt;I have tried using Update Occurrence, Update Instances:, Annotate as per PM Ordering, Annotate as per page ordering in the title blocks, Preserver Designator, and Auto-package Heterogeneous Part Using First Match, and they seem to have no effect.&amp;nbsp; I have tried &amp;quot;Advanced Annotation&amp;quot;&amp;nbsp; but it just opens and locks up.&amp;nbsp; The only button that works is the X to close the window. I even changed the reference designator for this part to UQ?A, UQ?B, UQ?C, UQ?D so that there would be no conflicts with any other &amp;quot;U&amp;quot; parts, and the output was pretty much the same.&amp;nbsp; I have OrCAD X Capture 23.1, but I have noticed this behavior in previous versions of OrCAD.&amp;nbsp;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;I&amp;#39;m beginning to think the only solution to this is to annotate it, then go in and manually change all 256 reference designators (4x64).&amp;nbsp;&lt;/p&gt;</description></item><item><title>Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/66059?ContentTypeID=0</link><pubDate>Wed, 10 Jun 2026 13:41:35 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:8385581c-5ec8-42d3-b4ef-68ce8d3c5516</guid><dc:creator>Jeet</dc:creator><slash:comments>2</slash:comments><comments>https://community.cadence.com/thread/66059?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Starting with version 25.1, you can save and reuse Design Template settings to maintain consistency across projects. Design Template allows you to define default settings for new schematic designs, including fonts for various schematic objects, title block information, page size, grid references, and more.&lt;/p&gt;
&lt;p&gt;To save and reuse Design Template settings, follow the given steps-&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Navigate to &lt;strong&gt;Options&lt;/strong&gt; &amp;gt; &lt;strong&gt;Design Template&lt;/strong&gt;.&lt;/li&gt;
&lt;li&gt;Customize the settings as required, including fonts, page size, title block, grid references, and other parameters.&lt;/li&gt;
&lt;li&gt;Once customization is complete, click Save. A dialog box will prompt you to save the configuration as a .dtp file at your preferred location.&lt;/li&gt;
&lt;li&gt;To apply the saved settings later, click Load in the Design Template dialog box and select the saved .dtp file from the desired location.&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;img style="max-height:480px;max-width:640px;" alt=" " src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1781098685237v1.png" /&gt;&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;This feature allows designers to reuse design properties across new schematic designs, eliminating the need for redundant redefinition. Additionally, it enables seamless sharing of template files among teams and ensures consistent formatting in&amp;nbsp;designs.&lt;/p&gt;</description></item><item><title>RE: Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/1408662?ContentTypeID=1</link><pubDate>Fri, 12 Jun 2026 19:28:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2698f6cc-f5ac-463f-988f-7f646a989f6e</guid><dc:creator>excellon1</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408662?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hi ULF&lt;/p&gt;
&lt;p&gt;Good idea on the font type. Just a FYI on this. At one time Orcad used to ship their own Orcad font for use in capture. It was in v16.3 or earlier.&lt;br /&gt;Perhaps you may have that install somewhere.&lt;br /&gt;&lt;br /&gt;Anyway, there is a fairly good difference between the number 0 and the letter o. The letter o is like a square with rounded off corners, it is also slightly bigger by a good margin than the number 0. Very easy to see the difference if printed or on the screen. the number 0 looks like ()&lt;br /&gt;&lt;br /&gt;do a search of the cadence folder for *.ttf to see if you have it. On windows I think you can just double click to install it to the Windows\Fonts folder or it could be copied manually too,&lt;/p&gt;
&lt;p&gt;I cant seem to post a pic of it here, but it does looks nice. &lt;/p&gt;
&lt;p&gt;Best regards.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>Debug the missing Part Number</title><link>https://community.cadence.com/thread/66064?ContentTypeID=0</link><pubDate>Fri, 12 Jun 2026 05:26:34 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:b703de1e-8f65-49da-8bd9-74be396abc29</guid><dc:creator>IshaS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/66064?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66064/debug-the-missing-part-number/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;
&lt;p&gt;In OrCAD X Capture CIS, the &lt;em&gt;Part Number&lt;/em&gt; column appears blank in Live BOM and Part Manager for existing components, even though the value exists in the database. The workspace is set to &lt;em&gt;Local&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;What is the most likely root cause?&lt;/strong&gt;&lt;br /&gt;&lt;br /&gt;&lt;img style="max-height:190px;max-width:202px;" height="190" src="https://community.cadence.com/resized-image/__size/404x380/__key/communityserver-discussions-components-files/109/pastedimage1781241779252v1.png" width="202" alt=" " /&gt;&amp;nbsp;&amp;nbsp;&lt;img style="max-height:258px;max-width:472px;" height="258" src="https://community.cadence.com/resized-image/__size/944x516/__key/communityserver-discussions-components-files/109/pastedimage1781241791101v2.png" width="472" alt=" " /&gt;&lt;br /&gt;&lt;br /&gt;&lt;/p&gt;
&lt;p&gt;&lt;img style="max-height:480px;max-width:640px;" src="https://community.cadence.com/resized-image/__size/1280x960/__key/communityserver-discussions-components-files/109/pastedimage1781241799829v3.png" alt=" " /&gt;&lt;/p&gt;
&lt;p&gt;A. The database is not connected properly, so Live BOM cannot fetch any properties for existing parts.&lt;br /&gt; B. In the CIS configuration, the &lt;em&gt;part_number&lt;/em&gt; field is mapped to a different OrCAD property name (for example, &lt;em&gt;PART_NUMBER_NEW&lt;/em&gt;) than the property name used by the existing schematic parts.&lt;br /&gt; C. Live BOM does not support displaying Part Number information when the workspace is set to &lt;em&gt;Local&lt;/em&gt;.&lt;br /&gt; D. The existing parts in the design must be re-placed from the CIS database before Live BOM can display the Part Number field.&lt;br /&gt;&lt;br /&gt;Try the scenario and share observations.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Happy Learning !!&lt;/p&gt;
&lt;/div&gt;</description></item><item><title>Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/66015?ContentTypeID=0</link><pubDate>Thu, 28 May 2026 10:52:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:63b48930-1dc9-4d15-88f0-33df42d03fb7</guid><dc:creator>Renu Vibha</dc:creator><slash:comments>30</slash:comments><comments>https://community.cadence.com/thread/66015?ContentTypeID=0</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Got questions on OrCAD Capture? Curious about what&amp;rsquo;s new, insights to resolve day to day workflow challenges? This is your chance to get answers&amp;mdash;directly from the expert.&lt;/p&gt;
&lt;p&gt;Join us here (&lt;a href="https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis"&gt;AllegroX Capture&lt;/a&gt; /or &lt;a href="https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl"&gt;Allegro TCL&lt;/a&gt;) , on&amp;nbsp;&lt;strong&gt;June 10, 2026 at 7:30-8:30PM IST &amp;nbsp;&lt;/strong&gt;for a live session, moderated by Cadence Expert, where you can interact, learn, and elevate your design skills.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;What&amp;rsquo;s in it for you?&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Get expert answers to your day-to-day design challenges&lt;/li&gt;
&lt;li&gt;Learn from practical use cases and peer discussions&lt;/li&gt;
&lt;li&gt;Engage in a dynamic session designed for maximum value and insights&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;&amp;nbsp;Key Topics:&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;strong&gt;Creating &amp;amp; Managing Variants (Part Manager)&lt;/strong&gt;&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;CIS Explorer&lt;/strong&gt; (Place Database Part, Link Database Part &amp;amp; more)&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;Don&amp;rsquo;t miss this opportunity to connect, learn, and grow with the community.&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;Bring your questions&lt;/li&gt;
&lt;li&gt;Share your experiences&lt;/li&gt;
&lt;li&gt;Be part of the energy&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;Let&amp;rsquo;s make this an engaging, insightful, and impactful session together!&lt;/p&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408656?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 15:07:06 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ac89259d-1b6f-4ccf-af05-ef75445dae69</guid><dc:creator>JR202606119023</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408656?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Helo mohit ,I am facing that issue in all the board designs .&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408655?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 15:05:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3290e07c-11f3-4a7a-a067-a8a559bfca90</guid><dc:creator>JR202606119023</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408655?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello Mohit, I am using &amp;quot;24.1-2024 S008 [1/12/2026] Windows SPB 64-bit Edition&amp;quot; i am unable to upload a snapshot.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408652?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 09:28:43 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:4f1fcde1-f469-4031-befb-97249c60d2e0</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408652?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello&lt;br /&gt;&lt;br /&gt;Thanks for your active participation in the session. I would request you to let your peers know about our interactive and engaging community forum. Apart from capture we have many other product buckets which they can explore to ask any query they have and connect with other designers too&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408651?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 09:24:59 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:bade9f11-b4f3-4cf4-b0bf-6b21fa594dfb</guid><dc:creator>MohitS</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408651?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;br /&gt;&lt;br /&gt;Can you please let me know which version and hotfix you are using. Also can you share a snapshot of the same?&lt;br /&gt;&lt;br /&gt;Are you facing this issue with a specific board design or the issue is with other designs too?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408650?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 08:28:11 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:c6d19b59-68f6-4076-9f6a-e973c949d5f0</guid><dc:creator>KS202606109251</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408650?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;thank you . Yes we have some scenario where we face some issues. I will share.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408649?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 08:06:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:3bce7d2e-b823-49d3-89fa-2abd8930da3f</guid><dc:creator>JR202606119023</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408649?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;span&gt;The top and bottom layers should be external, while other signals should be internal layers. Why isn&amp;#39;t this showing up in the Physical constraints, or do I need to enable something in the cross-section? &lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408648?ContentTypeID=1</link><pubDate>Thu, 11 Jun 2026 07:11:35 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22e1d2de-1a4c-48de-872f-1b1adb7ee90c</guid><dc:creator>JR202606119023</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408648?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span&gt;Hello,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;I am using Allegro X PCB Venture in that The top and bottom layers should be external, while other signals should be internal layers. Why isn&amp;#39;t this showing up in the Physical constraints, or do I need to enable something in the cross-section?&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Thanks&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Standardizing Design Settings in OrCAD X Capture CIS</title><link>https://community.cadence.com/thread/1408643?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 15:28:30 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:245ff557-519d-4246-bcf2-c114c988d55a</guid><dc:creator>Ulf K</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408643?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66059/standardizing-design-settings-in-orcad-x-capture-cis/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;This is a nice feature. May I humbly suggest that Cadence would consider including the font &amp;quot;Andale Mono&amp;quot; (Or Andale dot) in future releases. This font makes it easy to distinguish between captal O and the number 0 as the zero is displayed with a dot in its center. Some versions of zero uses a 0 with a forward slash / in it but that letter is the next to last letter in the Danish alphabet.&lt;/p&gt;
&lt;p&gt;My 5 eurocents.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408642?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 15:09:45 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ab793286-11eb-41b5-8ddb-3a2ddbf59a8a</guid><dc:creator>BC202603263145</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408642?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thanks!&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408641?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 15:09:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:aebfe098-a57d-493a-bf20-746742d2f39e</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408641?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;&lt;span class="TextRun SCXW72274577 BCX8" lang="EN-US" data-contrast="auto"&gt;&lt;span class="NormalTextRun SCXW72274577 BCX8"&gt;Thank you everyone for the great questions and engagement today. In case you have additional queries please feel free to post on the respective forums.&lt;/span&gt;&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408640?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 15:07:48 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:36a00e8f-58fc-400c-bbaa-b5fbefb90c42</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408640?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;In case you are driving constraints from schematic to layout you should define the constraints at early stage of schematic creatin. It is mandatory to have the constraints defined before the netlisting. Constraints can also be defined at PCB editor level and then can be imported back to schematic.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408639?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 15:05:09 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9e046ca2-1524-45e2-b893-9e37edd3bdee</guid><dc:creator>KS202606109251</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408639?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thank you for the responses&amp;hellip;. I am a student&amp;hellip; that&amp;rsquo;s why so many questions &amp;hellip;. This was a very good opportunity to interact.&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408638?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:56:01 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1e56a023-8dae-4bcc-b580-6b0cfb84caa4</guid><dc:creator>KS202606109251</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408638?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thank you &amp;hellip;. One last question&amp;hellip;. How early should we define electrical and physical constraints in OrCad Capture using Constraint Manager?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408637?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:55:16 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2d6f2833-3741-4f42-a1d0-d0145f62d7a7</guid><dc:creator>MohitS</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408637?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;br /&gt;There could be many&amp;nbsp;challenges with respect to net connectivity across &lt;span&gt;hierarchical&amp;nbsp;&lt;/span&gt;levels. These include port mismatches, global nets issues, missing hierarchical pins. Are there some specific scenarios where you face any difficulty or challenge while working with a hierarchical design?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408636?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:53:20 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e941786a-6462-446c-b193-14e261f929ea</guid><dc:creator>CF202606104231</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408636?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;thank you, it helps&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408635?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:50:47 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:282516a3-c7cc-45e5-88d9-0c0cb53a4835</guid><dc:creator>MohitS</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408635?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;br /&gt;&lt;br /&gt;Thanks for your query&lt;br /&gt;&lt;br /&gt;In case you want to add a custom property to your CIS BOM report, you have to add it through BOM configuration window. To add custom properties you need to go to Reports&amp;gt;CIS BOM and BOM window will open up. Under the selected properties field type in the custom property name and add it to the output format window. Once added the property will transfer to your BOM&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408634?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:50:16 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:ece34f27-c610-412a-b4c4-ff54dbd64448</guid><dc:creator>KS202606109251</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408634?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Thank you ..&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408633?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:47:26 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:9904a3fc-211f-4e30-9f9e-309aac449fc6</guid><dc:creator>MohitS</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408633?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;div&gt;Hierarchical schematics improve scalability by enabling &lt;strong&gt;modular design, reuse, and structured signal management&lt;/strong&gt;, making large designs easier to maintain, debug, and collaborate on&amp;mdash;whereas flat schematics become harder to manage as complexity increases.&lt;br /&gt;&lt;br /&gt;&lt;/div&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408631?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:43:26 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:f375f261-3aa3-475f-b9db-81ceeb387b1d</guid><dc:creator>KS202606109251</dc:creator><slash:comments>1</slash:comments><comments>https://community.cadence.com/thread/1408631?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;What challenges should we watch for she managing net connectivity across hierarchical levels?&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: Join us on Wednesday June 10, 2026 for a live “Ask Me Anything” Dedicated Expert Session: OrCAD Capture</title><link>https://community.cadence.com/thread/1408630?ContentTypeID=1</link><pubDate>Wed, 10 Jun 2026 14:42:50 GMT</pubDate><guid isPermaLink="false">75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:e236af49-9a6c-479b-ac5a-1c9f187c1cb8</guid><dc:creator>MohitS</dc:creator><slash:comments>0</slash:comments><comments>https://community.cadence.com/thread/1408630?ContentTypeID=1</comments><wfw:commentRss>https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/66015/join-us-on-wednesday-june-10-2026-for-a-live-ask-me-anything-dedicated-expert-session-orcad-capture/rss?ContentTypeId=0</wfw:commentRss><description>&lt;p&gt;Hello,&lt;br /&gt;&lt;br /&gt;Capture supports all the databases which are ODBC compliant. If a database can be configured with ODBC, capture will support that. Let me know in case you have any additional queries on this&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>